| Message ID | 20220908155243.687143-1-stuart.menefy@mathembedded.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | drm/meson: Fix OSD1 RGB to YCbCr coefficient | expand |
Hi ! On 08/09/2022 17:52, Stuart Menefy wrote: > VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12, > not 16-28. Thanks, Good catch ! > > Without this the output tends to have a pink hue, changing it results > in better color accuracy. Indeed, it was a regular issue reported. > > The vendor kernel doesn't use this register. However the code which > sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. There is a slightly > different style of registers for configuring some of the other matrices, > which do use bits 16-28 for this coefficient, but those have names > ending in MATRIX_COEF22_30, and this is not one of those. > Fixes: 728883948b0d ("drm/meson: Add G12A Support for VIU setup") > Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com> > --- > drivers/gpu/drm/meson/meson_viu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c > index 51df4de..876ffe0 100644 > --- a/drivers/gpu/drm/meson/meson_viu.c > +++ b/drivers/gpu/drm/meson/meson_viu.c > @@ -94,7 +94,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv, > priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); > writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), > priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); > - writel((m[11] & 0x1fff) << 16, > + writel((m[11] & 0x1fff), > priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); > > writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Hi, On Thu, 8 Sep 2022 16:52:43 +0100, Stuart Menefy wrote: > VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12, > not 16-28. > > Without this the output tends to have a pink hue, changing it results > in better color accuracy. > > The vendor kernel doesn't use this register. However the code which > sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. There is a slightly > different style of registers for configuring some of the other matrices, > which do use bits 16-28 for this coefficient, but those have names > ending in MATRIX_COEF22_30, and this is not one of those. > > [...] Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes) [1/1] drm/meson: Fix OSD1 RGB to YCbCr coefficient https://cgit.freedesktop.org/drm/drm-misc/commit/?id=6463d3930ba5b6addcfc8f80a4543976a2fc7656
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index 51df4de..876ffe0 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -94,7 +94,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); - writel((m[11] & 0x1fff) << 16, + writel((m[11] & 0x1fff), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12, not 16-28. Without this the output tends to have a pink hue, changing it results in better color accuracy. The vendor kernel doesn't use this register. However the code which sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. There is a slightly different style of registers for configuring some of the other matrices, which do use bits 16-28 for this coefficient, but those have names ending in MATRIX_COEF22_30, and this is not one of those. Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com> --- drivers/gpu/drm/meson/meson_viu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)