| Message ID | 20220913061817.22564-8-zong.li@sifive.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | da29dbcda49d60f34055df19bd4783b889fc7dfc |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | Use composable cache instead of L2 cache | expand |
On 13/09/2022 07:18, Zong Li wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Greentime Hu <greentime.hu@sifive.com> > > There are no standard CSR registers to provide cache information, the > way for RISC-V is to get this information from DT. sysconf syscall > could use them to get information of cache through AUX vector. > > The result of 'getconf -a|grep -i cache' as follows: > LEVEL1_ICACHE_SIZE 32768 > LEVEL1_ICACHE_ASSOC 2 > LEVEL1_ICACHE_LINESIZE 64 > LEVEL1_DCACHE_SIZE 32768 > LEVEL1_DCACHE_ASSOC 4 > LEVEL1_DCACHE_LINESIZE 64 > LEVEL2_CACHE_SIZE 524288 > LEVEL2_CACHE_ASSOC 8 > LEVEL2_CACHE_LINESIZE 64 > LEVEL3_CACHE_SIZE 4194304 > LEVEL3_CACHE_ASSOC 16 > LEVEL3_CACHE_LINESIZE 64 > LEVEL4_CACHE_SIZE 0 > LEVEL4_CACHE_ASSOC 0 > LEVEL4_CACHE_LINESIZE 0 > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Zong Li <zong.li@sifive.com> > Suggested-by: Zong Li <zong.li@sifive.com> > --- This _looks_ completely sane to me, but it is well beyond my paygrade... FWIW: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > arch/riscv/include/asm/elf.h | 4 ++++ > arch/riscv/include/uapi/asm/auxvec.h | 4 +++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h > index 14fc7342490b..e7acffdf21d2 100644 > --- a/arch/riscv/include/asm/elf.h > +++ b/arch/riscv/include/asm/elf.h > @@ -99,6 +99,10 @@ do { \ > get_cache_size(2, CACHE_TYPE_UNIFIED)); \ > NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ > get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ > + NEW_AUX_ENT(AT_L3_CACHESIZE, \ > + get_cache_size(3, CACHE_TYPE_UNIFIED)); \ > + NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, \ > + get_cache_geometry(3, CACHE_TYPE_UNIFIED)); \ > } while (0) > #define ARCH_HAS_SETUP_ADDITIONAL_PAGES > struct linux_binprm; > diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h > index 32c73ba1d531..fb187a33ce58 100644 > --- a/arch/riscv/include/uapi/asm/auxvec.h > +++ b/arch/riscv/include/uapi/asm/auxvec.h > @@ -30,8 +30,10 @@ > #define AT_L1D_CACHEGEOMETRY 43 > #define AT_L2_CACHESIZE 44 > #define AT_L2_CACHEGEOMETRY 45 > +#define AT_L3_CACHESIZE 46 > +#define AT_L3_CACHEGEOMETRY 47 > > /* entries in ARCH_DLINFO */ > -#define AT_VECTOR_SIZE_ARCH 7 > +#define AT_VECTOR_SIZE_ARCH 9 > > #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ > -- > 2.17.1 >
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index 14fc7342490b..e7acffdf21d2 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -99,6 +99,10 @@ do { \ get_cache_size(2, CACHE_TYPE_UNIFIED)); \ NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L3_CACHESIZE, \ + get_cache_size(3, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, \ + get_cache_geometry(3, CACHE_TYPE_UNIFIED)); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h index 32c73ba1d531..fb187a33ce58 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -30,8 +30,10 @@ #define AT_L1D_CACHEGEOMETRY 43 #define AT_L2_CACHESIZE 44 #define AT_L2_CACHEGEOMETRY 45 +#define AT_L3_CACHESIZE 46 +#define AT_L3_CACHEGEOMETRY 47 /* entries in ARCH_DLINFO */ -#define AT_VECTOR_SIZE_ARCH 7 +#define AT_VECTOR_SIZE_ARCH 9 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */