| Message ID | 20220914143648.74022-1-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: move riscv_cbom_block_size to the correct #ifdef block | expand |
On Wed, Sep 14, 2022 at 8:07 PM Heiko Stuebner <heiko@sntech.de> wrote: > > riscv_cbom_block_size is used by all current non-coherent dma operations, > not only the zicbom variant. So move it over the block also containing > the riscv_noncoherent_supported() prototype. At the moment, only non-coherent DMA operations use riscv_cbom_block_size but soon we have other parties using it as well. For example, the RISC-V PMEM support and KVM RISC-V Zicbom support. I am not sure if this is the right thing to do. Regards, Anup > > Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > arch/riscv/include/asm/cacheflush.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index a89c005b4bbf..5c16d901d3da 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); > #endif /* CONFIG_SMP */ > > #ifdef CONFIG_RISCV_ISA_ZICBOM > -extern unsigned int riscv_cbom_block_size; > void riscv_init_cbom_blocksize(void); > #else > static inline void riscv_init_cbom_blocksize(void) { } > #endif > > #ifdef CONFIG_RISCV_DMA_NONCOHERENT > +extern unsigned int riscv_cbom_block_size; > void riscv_noncoherent_supported(void); > #endif > > -- > 2.35.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 14/09/2022 15:46, Anup Patel wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Wed, Sep 14, 2022 at 8:07 PM Heiko Stuebner <heiko@sntech.de> wrote: >> >> riscv_cbom_block_size is used by all current non-coherent dma operations, >> not only the zicbom variant. So move it over the block also containing >> the riscv_noncoherent_supported() prototype. > > At the moment, only non-coherent DMA operations use riscv_cbom_block_size > but soon we have other parties using it as well. For example, the RISC-V PMEM > support and KVM RISC-V Zicbom support. > > I am not sure if this is the right thing to do. This is a fix for a current error reported by LKP. When said future users need to use it - they can move it to a better location IMO. Thanks, Conor. > > Regards, > Anup > >> >> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") >> Reported-by: kernel test robot <lkp@intel.com> >> Signed-off-by: Heiko Stuebner <heiko@sntech.de> >> --- >> arch/riscv/include/asm/cacheflush.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h >> index a89c005b4bbf..5c16d901d3da 100644 >> --- a/arch/riscv/include/asm/cacheflush.h >> +++ b/arch/riscv/include/asm/cacheflush.h >> @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); >> #endif /* CONFIG_SMP */ >> >> #ifdef CONFIG_RISCV_ISA_ZICBOM >> -extern unsigned int riscv_cbom_block_size; >> void riscv_init_cbom_blocksize(void); >> #else >> static inline void riscv_init_cbom_blocksize(void) { } >> #endif >> >> #ifdef CONFIG_RISCV_DMA_NONCOHERENT >> +extern unsigned int riscv_cbom_block_size; >> void riscv_noncoherent_supported(void); >> #endif >> >> -- >> 2.35.1 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Sep 14, 2022 at 8:24 PM <Conor.Dooley@microchip.com> wrote: > > On 14/09/2022 15:46, Anup Patel wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > On Wed, Sep 14, 2022 at 8:07 PM Heiko Stuebner <heiko@sntech.de> wrote: > >> > >> riscv_cbom_block_size is used by all current non-coherent dma operations, > >> not only the zicbom variant. So move it over the block also containing > >> the riscv_noncoherent_supported() prototype. > > > > At the moment, only non-coherent DMA operations use riscv_cbom_block_size > > but soon we have other parties using it as well. For example, the RISC-V PMEM > > support and KVM RISC-V Zicbom support. > > > > I am not sure if this is the right thing to do. > > This is a fix for a current error reported by LKP. > When said future users need to use it - they can move it to a better location > IMO. Why don't we move it to a better location now itself ? Regards, Anup > > Thanks, > Conor. > > > > > Regards, > > Anup > > > >> > >> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") > >> Reported-by: kernel test robot <lkp@intel.com> > >> Signed-off-by: Heiko Stuebner <heiko@sntech.de> > >> --- > >> arch/riscv/include/asm/cacheflush.h | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > >> index a89c005b4bbf..5c16d901d3da 100644 > >> --- a/arch/riscv/include/asm/cacheflush.h > >> +++ b/arch/riscv/include/asm/cacheflush.h > >> @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); > >> #endif /* CONFIG_SMP */ > >> > >> #ifdef CONFIG_RISCV_ISA_ZICBOM > >> -extern unsigned int riscv_cbom_block_size; > >> void riscv_init_cbom_blocksize(void); > >> #else > >> static inline void riscv_init_cbom_blocksize(void) { } > >> #endif > >> > >> #ifdef CONFIG_RISCV_DMA_NONCOHERENT > >> +extern unsigned int riscv_cbom_block_size; > >> void riscv_noncoherent_supported(void); > >> #endif > >> > >> -- > >> 2.35.1 > >> > >> > >> _______________________________________________ > >> linux-riscv mailing list > >> linux-riscv@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >
Am Mittwoch, 14. September 2022, 16:56:07 CEST schrieb Anup Patel: > On Wed, Sep 14, 2022 at 8:24 PM <Conor.Dooley@microchip.com> wrote: > > > > On 14/09/2022 15:46, Anup Patel wrote: > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > > On Wed, Sep 14, 2022 at 8:07 PM Heiko Stuebner <heiko@sntech.de> wrote: > > >> > > >> riscv_cbom_block_size is used by all current non-coherent dma operations, > > >> not only the zicbom variant. So move it over the block also containing > > >> the riscv_noncoherent_supported() prototype. > > > > > > At the moment, only non-coherent DMA operations use riscv_cbom_block_size > > > but soon we have other parties using it as well. For example, the RISC-V PMEM > > > support and KVM RISC-V Zicbom support. > > > > > > I am not sure if this is the right thing to do. > > > > This is a fix for a current error reported by LKP. > > When said future users need to use it - they can move it to a better location > > IMO. > > Why don't we move it to a better location now itself ? Probably because a fix should be a minimal set of changes, the breakage already exist and we're shortly before 6.0-rc6 ;-) If we start discussing now where to put it, we might end up releasing 6.0 with bugs. > > Regards, > Anup > > > > > Thanks, > > Conor. > > > > > > > > Regards, > > > Anup > > > > > >> > > >> Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") > > >> Reported-by: kernel test robot <lkp@intel.com> > > >> Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > >> --- > > >> arch/riscv/include/asm/cacheflush.h | 2 +- > > >> 1 file changed, 1 insertion(+), 1 deletion(-) > > >> > > >> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > > >> index a89c005b4bbf..5c16d901d3da 100644 > > >> --- a/arch/riscv/include/asm/cacheflush.h > > >> +++ b/arch/riscv/include/asm/cacheflush.h > > >> @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); > > >> #endif /* CONFIG_SMP */ > > >> > > >> #ifdef CONFIG_RISCV_ISA_ZICBOM > > >> -extern unsigned int riscv_cbom_block_size; > > >> void riscv_init_cbom_blocksize(void); > > >> #else > > >> static inline void riscv_init_cbom_blocksize(void) { } > > >> #endif > > >> > > >> #ifdef CONFIG_RISCV_DMA_NONCOHERENT > > >> +extern unsigned int riscv_cbom_block_size; > > >> void riscv_noncoherent_supported(void); > > >> #endif > > >> > > >> -- > > >> 2.35.1 > > >> > > >> > > >> _______________________________________________ > > >> linux-riscv mailing list > > >> linux-riscv@lists.infradead.org > > >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > >
On 14/09/2022 15:36, Heiko Stuebner wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > riscv_cbom_block_size is used by all current non-coherent dma operations, > not only the zicbom variant. So move it over the block also containing > the riscv_noncoherent_supported() prototype. > > Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") > Reported-by: kernel test robot <lkp@intel.com> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> I accidentally fetched palmers repo rather than riscv & noticed he pushed a fix there for this too: https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=zicbom-fix I think Palmer's solution is slightly nicer, but to me either makes little difference, just getting things squared away for 6.0 is all I care about at this point. Either this or the one on Palmer's branch is: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/include/asm/cacheflush.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > index a89c005b4bbf..5c16d901d3da 100644 > --- a/arch/riscv/include/asm/cacheflush.h > +++ b/arch/riscv/include/asm/cacheflush.h > @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); > #endif /* CONFIG_SMP */ > > #ifdef CONFIG_RISCV_ISA_ZICBOM > -extern unsigned int riscv_cbom_block_size; > void riscv_init_cbom_blocksize(void); > #else > static inline void riscv_init_cbom_blocksize(void) { } > #endif > > #ifdef CONFIG_RISCV_DMA_NONCOHERENT > +extern unsigned int riscv_cbom_block_size; > void riscv_noncoherent_supported(void); > #endif > > -- > 2.35.1 >
Hi, Am Mittwoch, 14. September 2022, 21:32:01 CEST schrieb Conor.Dooley@microchip.com: > On 14/09/2022 15:36, Heiko Stuebner wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > riscv_cbom_block_size is used by all current non-coherent dma operations, > > not only the zicbom variant. So move it over the block also containing > > the riscv_noncoherent_supported() prototype. > > > > Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") > > Reported-by: kernel test robot <lkp@intel.com> > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > I accidentally fetched palmers repo rather than riscv & noticed he > pushed a fix there for this too: > https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=zicbom-fix > > I think Palmer's solution is slightly nicer, but to me either makes > little difference, just getting things squared away for 6.0 is all > I care about at this point. yeah, Palmer's solution is nice and incidentially should also not only make LKP happier but maybe also Anup in one go :-) . So I'd guess disregard this patch and move Palmer's patch over? Heiko > > Either this or the one on Palmer's branch is: > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > --- > > arch/riscv/include/asm/cacheflush.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h > > index a89c005b4bbf..5c16d901d3da 100644 > > --- a/arch/riscv/include/asm/cacheflush.h > > +++ b/arch/riscv/include/asm/cacheflush.h > > @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); > > #endif /* CONFIG_SMP */ > > > > #ifdef CONFIG_RISCV_ISA_ZICBOM > > -extern unsigned int riscv_cbom_block_size; > > void riscv_init_cbom_blocksize(void); > > #else > > static inline void riscv_init_cbom_blocksize(void) { } > > #endif > > > > #ifdef CONFIG_RISCV_DMA_NONCOHERENT > > +extern unsigned int riscv_cbom_block_size; > > void riscv_noncoherent_supported(void); > > #endif > > > > -- > > 2.35.1 > > > >
On Wed, 14 Sep 2022 15:19:51 PDT (-0700), heiko@sntech.de wrote: > Hi, > > Am Mittwoch, 14. September 2022, 21:32:01 CEST schrieb Conor.Dooley@microchip.com: >> On 14/09/2022 15:36, Heiko Stuebner wrote: >> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> > >> > riscv_cbom_block_size is used by all current non-coherent dma operations, >> > not only the zicbom variant. So move it over the block also containing >> > the riscv_noncoherent_supported() prototype. >> > >> > Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") >> > Reported-by: kernel test robot <lkp@intel.com> >> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> >> >> I accidentally fetched palmers repo rather than riscv & noticed he >> pushed a fix there for this too: >> https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=zicbom-fix >> >> I think Palmer's solution is slightly nicer, but to me either makes >> little difference, just getting things squared away for 6.0 is all >> I care about at this point. > > yeah, Palmer's solution is nice and incidentially should also > not only make LKP happier but maybe also Anup in one go :-) . > > So I'd guess disregard this patch and move Palmer's patch over? OK, I'll go post mine and then merge it -- I was writing it at Plumbers, I guess I forgot to send it. > > > Heiko > >> >> Either this or the one on Palmer's branch is: >> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> >> > --- >> > arch/riscv/include/asm/cacheflush.h | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h >> > index a89c005b4bbf..5c16d901d3da 100644 >> > --- a/arch/riscv/include/asm/cacheflush.h >> > +++ b/arch/riscv/include/asm/cacheflush.h >> > @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); >> > #endif /* CONFIG_SMP */ >> > >> > #ifdef CONFIG_RISCV_ISA_ZICBOM >> > -extern unsigned int riscv_cbom_block_size; >> > void riscv_init_cbom_blocksize(void); >> > #else >> > static inline void riscv_init_cbom_blocksize(void) { } >> > #endif >> > >> > #ifdef CONFIG_RISCV_DMA_NONCOHERENT >> > +extern unsigned int riscv_cbom_block_size; >> > void riscv_noncoherent_supported(void); >> > #endif >> > >> > -- >> > 2.35.1 >> > >> >>
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index a89c005b4bbf..5c16d901d3da 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -43,13 +43,13 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ #ifdef CONFIG_RISCV_ISA_ZICBOM -extern unsigned int riscv_cbom_block_size; void riscv_init_cbom_blocksize(void); #else static inline void riscv_init_cbom_blocksize(void) { } #endif #ifdef CONFIG_RISCV_DMA_NONCOHERENT +extern unsigned int riscv_cbom_block_size; void riscv_noncoherent_supported(void); #endif
riscv_cbom_block_size is used by all current non-coherent dma operations, not only the zicbom variant. So move it over the block also containing the riscv_noncoherent_supported() prototype. Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/include/asm/cacheflush.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)