diff mbox series

[13/19] drm/i915/perf: Add Wa_16010703925:dg2

Message ID 20220823204155.8178-14-umesh.nerlige.ramappa@intel.com (mailing list archive)
State New, archived
Headers show
Series Add DG2 OA support | expand

Commit Message

Umesh Nerlige Ramappa Aug. 23, 2022, 8:41 p.m. UTC 
On DG2 A0, the OAR report format is buggy. Workaround is to not use it
for A0. For A0, remove the OAR format from the bitmask of supported
formats.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Dixit, Ashutosh Sept. 16, 2022, 1:08 a.m. UTC | #1 
On Tue, 23 Aug 2022 13:41:49 -0700, Umesh Nerlige Ramappa wrote:
>
> On DG2 A0, the OAR report format is buggy. Workaround is to not use it
> for A0. For A0, remove the OAR format from the bitmask of supported
> formats.

Are we going to support A0 upstream? If we are this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 167e7355980a..a28f07923d8f 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4741,6 +4741,11 @@ static void oa_init_supported_formats(struct i915_perf *perf)
>	default:
>		MISSING_CASE(platform);
>	}
> +
> +	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
> +		/* Wa_16010703925:dg2 */
> +		clear_bit(I915_OAR_FORMAT_A36u64_B8_C8, perf->format_mask);
> +	}
>  }
>
>  static void i915_perf_init_info(struct drm_i915_private *i915)
> --
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 167e7355980a..a28f07923d8f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4741,6 +4741,11 @@  static void oa_init_supported_formats(struct i915_perf *perf)
 	default:
 		MISSING_CASE(platform);
 	}
+
+ 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
+		/* Wa_16010703925:dg2 */
+		clear_bit(I915_OAR_FORMAT_A36u64_B8_C8, perf->format_mask);
+ 	}
 }
 
 static void i915_perf_init_info(struct drm_i915_private *i915)