| Message ID | 20220919143123.28250-1-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [V1] PCI: dwc: Fixes N_FTS setup | expand |
In subject, "Fix" (not "Fixes") so it's an imperative verb. Maybe "Fix n_fts[] array overrun" to be more specific. On Mon, Sep 19, 2022 at 08:01:23PM +0530, Vidya Sagar wrote: > commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup") > unnecessarily uses pci->link_gen in deriving the index to the Not just "unnecessarily"; using pci->link_gen is *incorrect* since only [0] and [1] are defined. > n_fts[] array also introducing the issue of accessing beyond the > boundaries of array for greater than Gen-2 speeds. This change fixes > that issue. > > Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup") > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index c6725c519a47..9e4d96e5a3f5 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -641,7 +641,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > if (pci->n_fts[1]) { > val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > val &= ~PORT_LOGIC_N_FTS_MASK; > - val |= pci->n_fts[pci->link_gen - 1]; > + val |= pci->n_fts[1]; > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > } > > -- > 2.17.1 >
On Mon, Sep 19, 2022, Vidya Sagar <vidyas@nvidia.com> wrote: > > commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup") > unnecessarily uses pci->link_gen in deriving the index to the > n_fts[] array also introducing the issue of accessing beyond the > boundaries of array for greater than Gen-2 speeds. This change fixes > that issue. > > Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup") > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Please send a V2 patch that addresses Bjorn's feedback. Thank you. Best regards, Jingoo Han > --- > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index c6725c519a47..9e4d96e5a3f5 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -641,7 +641,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > if (pci->n_fts[1]) { > val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > val &= ~PORT_LOGIC_N_FTS_MASK; > - val |= pci->n_fts[pci->link_gen - 1]; > + val |= pci->n_fts[1]; > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > } > > -- > 2.17.1 >
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c6725c519a47..9e4d96e5a3f5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -641,7 +641,7 @@ void dw_pcie_setup(struct dw_pcie *pci) if (pci->n_fts[1]) { val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val &= ~PORT_LOGIC_N_FTS_MASK; - val |= pci->n_fts[pci->link_gen - 1]; + val |= pci->n_fts[1]; dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); }
commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup") unnecessarily uses pci->link_gen in deriving the index to the n_fts[] array also introducing the issue of accessing beyond the boundaries of array for greater than Gen-2 speeds. This change fixes that issue. Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- drivers/pci/controller/dwc/pcie-designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)