diff mbox series

[14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field

Message ID 20220920090038.15133-15-chunfeng.yun@mediatek.com
State Accepted
Commit 993aa53ed076a987842be2943dba46b6099d8ec3
Headers show
Series unify register access and macros | expand

Commit Message

Chunfeng Yun Sept. 20, 2022, 9 a.m. UTC 
Use FIELD_PREP() macro to prepare bits field value, then no need define
macros of bits offset.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

Comments

AngeloGioacchino Del Regno Sept. 21, 2022, 8:14 a.m. UTC | #1 
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use FIELD_PREP() macro to prepare bits field value, then no need define
> macros of bits offset.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
diff mbox series

Patch

diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 5c257d67d7be..1e2ad617e8e3 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -153,15 +153,20 @@  static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
 	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
 				RG_DSI_VOUT_MSK |
 				RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
-				(4 << 20) | (4 << 17) | (4 << 14) |
-				(4 << 11) | (4 << 8) | (4 << 5) |
+				FIELD_PREP(RG_DSI_V02_SEL, 4) |
+				FIELD_PREP(RG_DSI_V032_SEL, 4) |
+				FIELD_PREP(RG_DSI_V04_SEL, 4) |
+				FIELD_PREP(RG_DSI_V072_SEL, 4) |
+				FIELD_PREP(RG_DSI_V10_SEL, 4) |
+				FIELD_PREP(RG_DSI_V12_SEL, 4) |
 				RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
 
 	usleep_range(30, 100);
 
 	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
 				RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
-				(8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
+				FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) |
+				RG_DSI_LNT_HS_BIAS_EN);
 
 	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
 			     RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
@@ -177,7 +182,8 @@  static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
 	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
 				RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
 				RG_DSI_MPPLL_PREDIV,
-				(txdiv0 << 3) | (txdiv1 << 5));
+				FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) |
+				FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1));
 
 	/*
 	 * PLL PCW config