| Message ID | 20220809172017.215412-1-aouledameur@baylibre.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | spi: amlogic: meson-spicc: Use pinctrl to drive CLK line when idle | expand |
Hi Amjad, On 09/08/2022 19:20, Amjad Ouled-Ameur wrote: > Between SPI transactions, all SPI pins are in HiZ state. When using the SS > signal from the SPICC controller it's not an issue because when the > transaction resumes all pins come back to the right state at the same time > as SS. > > The problem is when we use CS as a GPIO. In fact, between the GPIO CS > state change and SPI pins state change from idle, you can have a missing or > spurious clock transition. > > Set a bias on the clock depending on the clock polarity requested before CS > goes active, by passing a special "idle-low" and "idle-high" pinctrl state > and setting the right state at a start of a message. > > Amjad Ouled-Ameur (2): > spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI > signal states > spi: meson-spicc: Use pinctrl to drive CLK line when idle > > .../bindings/spi/amlogic,meson-gx-spicc.yaml | 15 +++++++ > arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++++ > drivers/spi/spi-meson-spicc.c | 39 ++++++++++++++++++- > 3 files changed, 67 insertions(+), 1 deletion(-) > Will you send a v2 with comments adresses ?
Hi Neil, On 9/27/22 10:30, Neil Armstrong wrote: > Hi Amjad, > > On 09/08/2022 19:20, Amjad Ouled-Ameur wrote: >> Between SPI transactions, all SPI pins are in HiZ state. When using >> the SS >> signal from the SPICC controller it's not an issue because when the >> transaction resumes all pins come back to the right state at the same >> time >> as SS. >> >> The problem is when we use CS as a GPIO. In fact, between the GPIO CS >> state change and SPI pins state change from idle, you can have a >> missing or >> spurious clock transition. >> >> Set a bias on the clock depending on the clock polarity requested >> before CS >> goes active, by passing a special "idle-low" and "idle-high" pinctrl >> state >> and setting the right state at a start of a message. >> >> Amjad Ouled-Ameur (2): >> spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI >> signal states >> spi: meson-spicc: Use pinctrl to drive CLK line when idle >> >> .../bindings/spi/amlogic,meson-gx-spicc.yaml | 15 +++++++ >> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++++ >> drivers/spi/spi-meson-spicc.c | 39 ++++++++++++++++++- >> 3 files changed, 67 insertions(+), 1 deletion(-) >> > > Will you send a v2 with comments adresses ? Planning to send it soon, thank you for the review. Regards, Amjad
Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message. Amjad Ouled-Ameur (2): spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states spi: meson-spicc: Use pinctrl to drive CLK line when idle .../bindings/spi/amlogic,meson-gx-spicc.yaml | 15 +++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++++ drivers/spi/spi-meson-spicc.c | 39 ++++++++++++++++++- 3 files changed, 67 insertions(+), 1 deletion(-)