| Message ID | 20220823183319.3314940-1-mail@conchuod.ie (mailing list archive) |
|---|---|
| Headers | show |
| Series | Fix dt-validate issues on qemu dtbdumps due to dt-bindings | expand |
On 23/08/2022 19:33, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The device trees produced automatically for the virt and spike machines > fail dt-validate on several grounds. Some of these need to be fixed in > the linux kernel's dt-bindings, but others are caused by bugs in QEMU. > > Patches been sent that fix the QEMU issues [0], but a couple of them > need to be fixed in the kernel's dt-bindings. The first patches add > compatibles for "riscv,{clint,plic}0" which are present in drivers and > the auto generated QEMU dtbs. The final patch should be ignored for all > serious purposes unless you want to wash your eyes out afterwards, but > JIC the versioned extensions ever come up, it's there. Been no movement here for a few weeks, I assume things are waiting for either Acks from Palmer or for him to take the patches directly? Thanks, Conor. > > Thanks to Rob Herring for reporting these issues [1], > Conor. > > To reproduce the errors: > ./build/qemu-system-riscv64 -nographic -machine virt,dumpdtb=qemu.dtb > dt-validate -p /path/to/linux/kernel/Documentation/devicetree/bindings/processed-schema.json qemu.dtb > (The processed schema needs to be generated first) > > 0 - https://lore.kernel.org/linux-riscv/20220810184612.157317-1-mail@conchuod.ie/ > 1 - https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ > > Changes since v3: > - dropped the charset restrictions for standard multiletter isa extensions > > Changes since v2: > - removed the extra patches from the directory > > Changes since v1: > - drop the "legacy systems" bit from the binding descriptions > - convert to a regex for the isa string > > Conor Dooley (4): > dt-bindings: timer: sifive,clint: add legacy riscv compatible > dt-bindings: interrupt-controller: sifive,plic: add legacy riscv > compatible > dt-bindings: riscv: add new riscv,isa strings for emulators > dt-bindings: riscv: isa string bonus content > > .../sifive,plic-1.0.0.yaml | 5 +++++ > .../devicetree/bindings/riscv/cpus.yaml | 9 ++++++--- > .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------ > 3 files changed, 23 insertions(+), 9 deletions(-) > > > base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
On Tue, 23 Aug 2022 19:33:16 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The device trees produced automatically for the virt and spike machines > fail dt-validate on several grounds. Some of these need to be fixed in > the linux kernel's dt-bindings, but others are caused by bugs in QEMU. > > Patches been sent that fix the QEMU issues [0], but a couple of them > need to be fixed in the kernel's dt-bindings. The first patches add > compatibles for "riscv,{clint,plic}0" which are present in drivers and > the auto generated QEMU dtbs. The final patch should be ignored for all > serious purposes unless you want to wash your eyes out afterwards, but > JIC the versioned extensions ever come up, it's there. > > [...] Applied, thanks! [1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible https://git.kernel.org/palmer/c/826249942679 [2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible https://git.kernel.org/palmer/c/6e965c9bd738 [3/4] dt-bindings: riscv: add new riscv,isa strings for emulators https://git.kernel.org/palmer/c/299824e68bd0 Best regards,
From: Conor Dooley <conor.dooley@microchip.com> The device trees produced automatically for the virt and spike machines fail dt-validate on several grounds. Some of these need to be fixed in the linux kernel's dt-bindings, but others are caused by bugs in QEMU. Patches been sent that fix the QEMU issues [0], but a couple of them need to be fixed in the kernel's dt-bindings. The first patches add compatibles for "riscv,{clint,plic}0" which are present in drivers and the auto generated QEMU dtbs. The final patch should be ignored for all serious purposes unless you want to wash your eyes out afterwards, but JIC the versioned extensions ever come up, it's there. Thanks to Rob Herring for reporting these issues [1], Conor. To reproduce the errors: ./build/qemu-system-riscv64 -nographic -machine virt,dumpdtb=qemu.dtb dt-validate -p /path/to/linux/kernel/Documentation/devicetree/bindings/processed-schema.json qemu.dtb (The processed schema needs to be generated first) 0 - https://lore.kernel.org/linux-riscv/20220810184612.157317-1-mail@conchuod.ie/ 1 - https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Changes since v3: - dropped the charset restrictions for standard multiletter isa extensions Changes since v2: - removed the extra patches from the directory Changes since v1: - drop the "legacy systems" bit from the binding descriptions - convert to a regex for the isa string Conor Dooley (4): dt-bindings: timer: sifive,clint: add legacy riscv compatible dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible dt-bindings: riscv: add new riscv,isa strings for emulators dt-bindings: riscv: isa string bonus content .../sifive,plic-1.0.0.yaml | 5 +++++ .../devicetree/bindings/riscv/cpus.yaml | 9 ++++++--- .../bindings/timer/sifive,clint.yaml | 18 ++++++++++++------ 3 files changed, 23 insertions(+), 9 deletions(-) base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868