| Message ID | 13a62ced1808546c1d398e2025cf85f4c94ae123.1664550870.git.thomas.lendacky@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Qemu SEV reduced-phys-bits fixes | expand |
* Tom Lendacky (thomas.lendacky@amd.com) wrote: > A guest only ever experiences, at most, 1 bit of reduced physical > addressing. Update the documentation to reflect this as well as change > the example value on the reduced-phys-bits option. > > Fixes: a9b4942f48 ("target/i386: add Secure Encrypted Virtualization (SEV) object") > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> > --- > qemu-options.hx | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/qemu-options.hx b/qemu-options.hx > index 913c71e38f..3396085cf0 100644 > --- a/qemu-options.hx > +++ b/qemu-options.hx > @@ -5391,7 +5391,7 @@ SRST > physical address space. The ``reduced-phys-bits`` is used to > provide the number of bits we loose in physical address space. > Similar to C-bit, the value is Host family dependent. On EPYC, > - the value should be 5. > + a guest will lose a maximum of 1 bit, so the value should be 1. > > The ``sev-device`` provides the device file to use for > communicating with the SEV firmware running inside AMD Secure > @@ -5426,7 +5426,7 @@ SRST > > # |qemu_system_x86| \\ > ...... \\ > - -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=5 \\ > + -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=1 \\ > -machine ...,memory-encryption=sev0 \\ > ..... > > -- > 2.37.3 > >
diff --git a/qemu-options.hx b/qemu-options.hx index 913c71e38f..3396085cf0 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -5391,7 +5391,7 @@ SRST physical address space. The ``reduced-phys-bits`` is used to provide the number of bits we loose in physical address space. Similar to C-bit, the value is Host family dependent. On EPYC, - the value should be 5. + a guest will lose a maximum of 1 bit, so the value should be 1. The ``sev-device`` provides the device file to use for communicating with the SEV firmware running inside AMD Secure @@ -5426,7 +5426,7 @@ SRST # |qemu_system_x86| \\ ...... \\ - -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=5 \\ + -object sev-guest,id=sev0,cbitpos=47,reduced-phys-bits=1 \\ -machine ...,memory-encryption=sev0 \\ .....
A guest only ever experiences, at most, 1 bit of reduced physical addressing. Update the documentation to reflect this as well as change the example value on the reduced-phys-bits option. Fixes: a9b4942f48 ("target/i386: add Secure Encrypted Virtualization (SEV) object") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- qemu-options.hx | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)