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[2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge

Message ID 20221019144640.9458-2-thippeswamy.havalige@amd.com (mailing list archive)
State Superseded
Headers show
Series [1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge | expand

Commit Message

Thippeswamy Havalige Oct. 19, 2022, 2:46 p.m. UTC 
Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
dt binding.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
---
 .../bindings/pci/xilinx-nwl-pcie.txt          |  73 -----------
 .../bindings/pci/xilinx-nwl-pcie.yaml         | 122 ++++++++++++++++++
 2 files changed, 122 insertions(+), 73 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml

Comments

Krzysztof Kozlowski Oct. 19, 2022, 3:13 p.m. UTC | #1 
On 19/10/2022 10:46, Thippeswamy Havalige wrote:
> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
> dt binding.
> 
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>

(...)

> diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml
> new file mode 100644
> index 000000000000..97a33e8cc171
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml
> @@ -0,0 +1,122 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/xilinx-nwl-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx NWL PCIe Root Port Bridge DT description

Same comments apply.

> +
> +maintainers:
> +  - Thippeswamy Havalige <thippesw@xilinx.com>

Use current email address.

> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    const: xlnx,nwl-pcie-2.11
> +
> +  reg:
> +    items:
> +      - description: PCIe bridge registers location.
> +      - description: PCIe Controller registers location.
> +      - description: PCIe Configuration space region.
> +
> +  reg-names:
> +    items:
> +      - const: breg
> +      - const: pcireg
> +      - const: cfg
> +
> +  interrupts:
> +    items:
> +      - description: msi0 interrupt asserted when an MSI is received
> +      - description: msi1 interrupt asserted when an MSI is received
> +      - description: interrupt asserted when a legacy interrupt is received
> +      - description: unused interrupt(dummy)
> +      - description: interrupt asserted when miscellaneous interrupt is received
> +
> +  interrupt-names:
> +    minItems: 5

maxItems instead

> +
> +  interrupt-map-mask:
> +    items:
> +      - const: 0
> +      - const: 0
> +      - const: 0
> +      - const: 7
> +
> +  "#interrupt-cells":
> +    const: 1
> +
> +  msi-controller:
> +    description: Identifies the node as an MSI controller.

If it is a MSI controller, shouldn't you reference
/schemas/interrupt-controller/msi-controller.yaml ?

> +
> +  msi-parent:
> +    description: MSI controller the device is capable of using.

msi-parent: true

> +
> +  interrupt-map:
> +    maxItems: 4
> +
> +  legacy-interrupt-controller:
> +    description: Interrupt controller node for handling legacy PCI interrupts.
> +    type: object

Same comments apply.

> +    properties:
> +      "#address-cells":
> +        const: 0
> +      "#interrupt-cells":
> +        const: 1
> +      "interrupt-controller": true
> +

what happened to clocks? You did not describe any changes in commit msg.

> +required:

compatible

> +  - reg
> +  - reg-names
> +  - interrupts
> +  - interrupt-names
> +  - "#interrupt-cells"
> +  - interrupt-map
> +  - msi-controller
> +  - msi-parent
> +  - interrupt-map-mask
> +  - legacy-interrupt-controller

Drop properties required by referenced schema.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +
> +    soc {
> +          #address-cells = <2>;
> +          #size-cells = <2>;
> +          nwl_pcie: pcie@fd0e0000 {
> +                     #address-cells = <3>;

Mess up indentation

Use 4 spaces for example indentation.

> +                     #size-cells = <2>;
> +                     compatible = "xlnx,nwl-pcie-2.11";

Same comments apply

> +                     #interrupt-cells = <1>;
> +                     msi-controller;
> +                     device_type = "pci";
> +                     interrupt-parent = <&gic>;
> +                     interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
> +                     interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
> +                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> +                     interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
> +                                     <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
> +                                     <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
> +                                     <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
> +
> +                     msi-parent = <&nwl_pcie>;
> +                     reg = <0x0 0xfd0e0000 0x0 0x1000>,
> +                           <0x0 0xfd480000 0x0 0x1000>,
> +                           <0x80 0x00000000 0x0 0x1000000>;

This is a second property in the list (followed by reg-names, ranges)

> +                     reg-names = "breg", "pcireg", "cfg";
> +                     ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000
> +                               0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
> +
> +                     pcie_intc: legacy-interrupt-controller {
> +                     interrupt-controller;

That's even worse...

> +                     #address-cells = <0>;
> +                     #interrupt-cells = <1>;
> +                     };
> +
> +           };
> +        };

Best regards,
Krzysztof
Rob Herring Oct. 19, 2022, 11:31 p.m. UTC | #2 
On Wed, 19 Oct 2022 20:16:40 +0530, Thippeswamy Havalige wrote:
> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
> dt binding.
> 
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> ---
>  .../bindings/pci/xilinx-nwl-pcie.txt          |  73 -----------
>  .../bindings/pci/xilinx-nwl-pcie.yaml         | 122 ++++++++++++++++++
>  2 files changed, 122 insertions(+), 73 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/


pcie@fd0e0000: Unevaluated properties are not allowed ('clocks', 'iommus', 'power-domains' were unexpected)
	arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dtb
	arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dtb
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
deleted file mode 100644
index f56f8c58c5d9..000000000000
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ /dev/null
@@ -1,73 +0,0 @@ 
-* Xilinx NWL PCIe Root Port Bridge DT description
-
-Required properties:
-- compatible: Should contain "xlnx,nwl-pcie-2.11"
-- #address-cells: Address representation for root ports, set to <3>
-- #size-cells: Size representation for root ports, set to <2>
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- reg: Should contain Bridge, PCIe Controller registers location,
-	configuration space, and length
-- reg-names: Must include the following entries:
-	"breg": bridge registers
-	"pcireg": PCIe controller registers
-	"cfg": configuration space region
-- device_type: must be "pci"
-- interrupts: Should contain NWL PCIe interrupt
-- interrupt-names: Must include the following entries:
-	"msi1, msi0": interrupt asserted when an MSI is received
-	"intx": interrupt asserted when a legacy interrupt is received
-	"misc": interrupt asserted when miscellaneous interrupt is received
-- interrupt-map-mask and interrupt-map: standard PCI properties to define the
-	mapping of the PCI interface to interrupt numbers.
-- ranges: ranges for the PCI memory regions (I/O space region is not
-	supported by hardware)
-	Please refer to the standard PCI bus binding document for a more
-	detailed explanation
-- msi-controller: indicates that this is MSI controller node
-- msi-parent:  MSI parent of the root complex itself
-- legacy-interrupt-controller: Interrupt controller device node for Legacy
-	interrupts
-	- interrupt-controller: identifies the node as an interrupt controller
-	- #interrupt-cells: should be set to 1
-	- #address-cells: specifies the number of cells needed to encode an
-		address. The value must be 0.
-
-Optional properties:
-- dma-coherent: present if DMA operations are coherent
-- clocks: Input clock specifier. Refer to common clock bindings
-
-Example:
-++++++++
-
-nwl_pcie: pcie@fd0e0000 {
-	#address-cells = <3>;
-	#size-cells = <2>;
-	compatible = "xlnx,nwl-pcie-2.11";
-	#interrupt-cells = <1>;
-	msi-controller;
-	device_type = "pci";
-	interrupt-parent = <&gic>;
-	interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
-	interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
-	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
-	interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
-			<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
-			<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
-			<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
-
-	msi-parent = <&nwl_pcie>;
-	reg = <0x0 0xfd0e0000 0x0 0x1000>,
-	      <0x0 0xfd480000 0x0 0x1000>,
-	      <0x80 0x00000000 0x0 0x1000000>;
-	reg-names = "breg", "pcireg", "cfg";
-	ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
-		  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
-
-	pcie_intc: legacy-interrupt-controller {
-		interrupt-controller;
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-	};
-
-};
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml
new file mode 100644
index 000000000000..97a33e8cc171
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml
@@ -0,0 +1,122 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/xilinx-nwl-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx NWL PCIe Root Port Bridge DT description
+
+maintainers:
+  - Thippeswamy Havalige <thippesw@xilinx.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: xlnx,nwl-pcie-2.11
+
+  reg:
+    items:
+      - description: PCIe bridge registers location.
+      - description: PCIe Controller registers location.
+      - description: PCIe Configuration space region.
+
+  reg-names:
+    items:
+      - const: breg
+      - const: pcireg
+      - const: cfg
+
+  interrupts:
+    items:
+      - description: msi0 interrupt asserted when an MSI is received
+      - description: msi1 interrupt asserted when an MSI is received
+      - description: interrupt asserted when a legacy interrupt is received
+      - description: unused interrupt(dummy)
+      - description: interrupt asserted when miscellaneous interrupt is received
+
+  interrupt-names:
+    minItems: 5
+
+  interrupt-map-mask:
+    items:
+      - const: 0
+      - const: 0
+      - const: 0
+      - const: 7
+
+  "#interrupt-cells":
+    const: 1
+
+  msi-controller:
+    description: Identifies the node as an MSI controller.
+
+  msi-parent:
+    description: MSI controller the device is capable of using.
+
+  interrupt-map:
+    maxItems: 4
+
+  legacy-interrupt-controller:
+    description: Interrupt controller node for handling legacy PCI interrupts.
+    type: object
+    properties:
+      "#address-cells":
+        const: 0
+      "#interrupt-cells":
+        const: 1
+      "interrupt-controller": true
+
+required:
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - "#interrupt-cells"
+  - interrupt-map
+  - msi-controller
+  - msi-parent
+  - interrupt-map-mask
+  - legacy-interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+
+    soc {
+          #address-cells = <2>;
+          #size-cells = <2>;
+          nwl_pcie: pcie@fd0e0000 {
+                     #address-cells = <3>;
+                     #size-cells = <2>;
+                     compatible = "xlnx,nwl-pcie-2.11";
+                     #interrupt-cells = <1>;
+                     msi-controller;
+                     device_type = "pci";
+                     interrupt-parent = <&gic>;
+                     interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
+                     interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
+                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                     interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+                                     <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+                                     <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+                                     <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+
+                     msi-parent = <&nwl_pcie>;
+                     reg = <0x0 0xfd0e0000 0x0 0x1000>,
+                           <0x0 0xfd480000 0x0 0x1000>,
+                           <0x80 0x00000000 0x0 0x1000000>;
+                     reg-names = "breg", "pcireg", "cfg";
+                     ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000
+                               0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
+
+                     pcie_intc: legacy-interrupt-controller {
+                     interrupt-controller;
+                     #address-cells = <0>;
+                     #interrupt-cells = <1>;
+                     };
+
+           };
+        };