diff mbox series

drm/i915/xelp: Add Wa_1806527549

Message ID 20221019142145.111024-1-gustavo.sousa@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/xelp: Add Wa_1806527549 | expand

Commit Message

Gustavo Sousa Oct. 19, 2022, 2:21 p.m. UTC 
Workaround to be applied to platforms using XE_LP graphics.

BSpec: 52890
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
 2 files changed, 8 insertions(+)

Comments

Gustavo Sousa Oct. 19, 2022, 4:09 p.m. UTC | #1 
On Wed, Oct 19, 2022 at 11:21:45AM -0300, Gustavo Sousa wrote:
> Workaround to be applied to platforms using XE_LP graphics.
> 
> BSpec: 52890
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 36d95b79022c..23844ba7e824 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -443,6 +443,7 @@
>  #define HIZ_CHICKEN				_MMIO(0x7018)
>  #define   CHV_HZ_8X8_MODE_IN_1X			REG_BIT(15)
>  #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
> +#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE	REG_BIT(13)
>  #define   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT(3)
>  
>  #define GEN8_L3CNTLREG				_MMIO(0x7034)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 63e1e6becf34..5cdec699ae04 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -660,6 +660,8 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>  static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>  				       struct i915_wa_list *wal)
>  {
> +	struct drm_i915_private *i915 = engine->i915;
> +
>  	gen12_ctx_gt_tuning_init(engine, wal);
>  
>  	/*
> @@ -693,6 +695,11 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	       FF_MODE2_GS_TIMER_MASK,
>  	       FF_MODE2_GS_TIMER_224,
>  	       0, false);
> +
> +	if (!IS_DG1(i915))
> +		/* Wa_1806527549 */
> +		wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
> +

Just realized this extra blank line... I will sent a v2 without it.

>  }
>  
>  static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
> -- 
> 2.38.0
>
Summers, Stuart Oct. 21, 2022, 4:03 a.m. UTC | #2 
On Wed, 2022-10-19 at 11:21 -0300, Gustavo Sousa wrote:
> Workaround to be applied to platforms using XE_LP graphics.
> 
> BSpec: 52890
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 36d95b79022c..23844ba7e824 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -443,6 +443,7 @@
>  #define HIZ_CHICKEN				_MMIO(0x7018)
>  #define   CHV_HZ_8X8_MODE_IN_1X			REG_BIT(15)
>  #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT
> (14)
> +#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE	REG_BIT(13)
>  #define   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT
> (3)
>  
>  #define GEN8_L3CNTLREG				_MMIO(0x7034)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 63e1e6becf34..5cdec699ae04 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -660,6 +660,8 @@ static void gen12_ctx_gt_tuning_init(struct
> intel_engine_cs *engine,
>  static void gen12_ctx_workarounds_init(struct intel_engine_cs
> *engine,
>  				       struct i915_wa_list *wal)
>  {
> +	struct drm_i915_private *i915 = engine->i915;
> +
>  	gen12_ctx_gt_tuning_init(engine, wal);
>  
>  	/*
> @@ -693,6 +695,11 @@ static void gen12_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>  	       FF_MODE2_GS_TIMER_MASK,
>  	       FF_MODE2_GS_TIMER_224,
>  	       0, false);
> +
> +	if (!IS_DG1(i915))

My reading of the spec here is that we should be applying this to DG1
as well. Why are you removing it there?

Also, it looks like this is conditional on a specific depth buffer, do
we need to take that into account here?

Thanks,
Stuart

> +		/* Wa_1806527549 */
> +		wa_masked_en(wal, HIZ_CHICKEN,
> HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
> +
>  }
>  
>  static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
Lucas De Marchi Oct. 21, 2022, 5:28 a.m. UTC | #3 
On Fri, Oct 21, 2022 at 04:03:20AM +0000, Stuart Summers wrote:
>On Wed, 2022-10-19 at 11:21 -0300, Gustavo Sousa wrote:
>> Workaround to be applied to platforms using XE_LP graphics.
>>
>> BSpec: 52890
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>>  2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 36d95b79022c..23844ba7e824 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -443,6 +443,7 @@
>>  #define HIZ_CHICKEN				_MMIO(0x7018)
>>  #define   CHV_HZ_8X8_MODE_IN_1X			REG_BIT(15)
>>  #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT
>> (14)
>> +#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE	REG_BIT(13)
>>  #define   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT
>> (3)
>>
>>  #define GEN8_L3CNTLREG				_MMIO(0x7034)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 63e1e6becf34..5cdec699ae04 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -660,6 +660,8 @@ static void gen12_ctx_gt_tuning_init(struct
>> intel_engine_cs *engine,
>>  static void gen12_ctx_workarounds_init(struct intel_engine_cs
>> *engine,
>>  				       struct i915_wa_list *wal)
>>  {
>> +	struct drm_i915_private *i915 = engine->i915;
>> +
>>  	gen12_ctx_gt_tuning_init(engine, wal);
>>
>>  	/*
>> @@ -693,6 +695,11 @@ static void gen12_ctx_workarounds_init(struct
>> intel_engine_cs *engine,
>>  	       FF_MODE2_GS_TIMER_MASK,
>>  	       FF_MODE2_GS_TIMER_224,
>>  	       0, false);
>> +
>> +	if (!IS_DG1(i915))
>
>My reading of the spec here is that we should be applying this to DG1
>as well. Why are you removing it there?

for me DG1 is marked as "no impact"


>Also, it looks like this is conditional on a specific depth buffer, do
>we need to take that into account here?

it was agreed with mesa to do this unconditionally, so it can be done in
i915 rather than in mesa as it doesn't appear to have side effects.

Lucas De Marchi

>
>Thanks,
>Stuart
>
>> +		/* Wa_1806527549 */
>> +		wa_masked_en(wal, HIZ_CHICKEN,
>> HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
>> +
>>  }
>>
>>  static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c..23844ba7e824 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -443,6 +443,7 @@ 
 #define HIZ_CHICKEN				_MMIO(0x7018)
 #define   CHV_HZ_8X8_MODE_IN_1X			REG_BIT(15)
 #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
+#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE	REG_BIT(13)
 #define   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT(3)
 
 #define GEN8_L3CNTLREG				_MMIO(0x7034)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 63e1e6becf34..5cdec699ae04 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -660,6 +660,8 @@  static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
 				       struct i915_wa_list *wal)
 {
+	struct drm_i915_private *i915 = engine->i915;
+
 	gen12_ctx_gt_tuning_init(engine, wal);
 
 	/*
@@ -693,6 +695,11 @@  static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
 	       FF_MODE2_GS_TIMER_MASK,
 	       FF_MODE2_GS_TIMER_224,
 	       0, false);
+
+	if (!IS_DG1(i915))
+		/* Wa_1806527549 */
+		wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
+
 }
 
 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,