| Message ID | 20220928-mdm9615-dt-schema-fixes-v4-3-dac2dfaac703@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm: qcom: mdm9615: first round of bindings and DT fixes | expand |
On 21.10.2022 11:06, Neil Armstrong wrote: > Fixes cpu@0: 'reg' is a required property from dtbs check. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi > index de36e4545e75..eaa3236f62db 100644 > --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi > +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi > @@ -27,6 +27,7 @@ cpus { > > cpu0: cpu@0 { > compatible = "arm,cortex-a5"; > + reg = <0>; > device_type = "cpu"; > next-level-cache = <&L2>; > }; >
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index de36e4545e75..eaa3236f62db 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -27,6 +27,7 @@ cpus { cpu0: cpu@0 { compatible = "arm,cortex-a5"; + reg = <0>; device_type = "cpu"; next-level-cache = <&L2>; };