diff mbox series

[RFC,6/8] target/riscv: delete redundant check for zcd instructions in decode_opc

Message ID 20220930012345.5248-7-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series support subsets of code size reduction extension | expand

Commit Message

Weiwei Li Sept. 30, 2022, 1:23 a.m. UTC
All the check for Zcd instructions have been done in their trans function

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/translate.c | 7 -------
 1 file changed, 7 deletions(-)

Comments

Alistair Francis Oct. 25, 2022, 3:39 a.m. UTC | #1
On Fri, Sep 30, 2022 at 11:28 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> All the check for Zcd instructions have been done in their trans function
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>  target/riscv/translate.c | 7 -------
>  1 file changed, 7 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 347bc913eb..a55b4a7849 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1087,13 +1087,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
>               ((opcode & 0xe003) == 0xe000) ||
>               ((opcode & 0xe003) == 0xe002))) {
>              gen_exception_illegal(ctx);
> -        } else if (!(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zcd ||
> -                     ctx->cfg_ptr->ext_zcmp || ctx->cfg_ptr->ext_zcmt) &&
> -                   (((opcode & 0xe003) == 0x2000) ||
> -                    ((opcode & 0xe003) == 0x2002) ||
> -                    ((opcode & 0xe003) == 0xa000) ||
> -                    ((opcode & 0xe003) == 0xa002))) {
> -            gen_exception_illegal(ctx);

It's probably best to never add this in the first place.

Remember that the extension can't be enabled until the last patch, so
it's ok if we don't support it all in one go

Alistair

>          } else {
>              ctx->opcode = opcode;
>              ctx->pc_succ_insn = ctx->base.pc_next + 2;
> --
> 2.25.1
>
>
Weiwei Li Oct. 25, 2022, 7:03 a.m. UTC | #2
On 2022/10/25 11:39, Alistair Francis wrote:
> On Fri, Sep 30, 2022 at 11:28 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> All the check for Zcd instructions have been done in their trans function
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/translate.c | 7 -------
>>   1 file changed, 7 deletions(-)
>>
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 347bc913eb..a55b4a7849 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -1087,13 +1087,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
>>                ((opcode & 0xe003) == 0xe000) ||
>>                ((opcode & 0xe003) == 0xe002))) {
>>               gen_exception_illegal(ctx);
>> -        } else if (!(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zcd ||
>> -                     ctx->cfg_ptr->ext_zcmp || ctx->cfg_ptr->ext_zcmt) &&
>> -                   (((opcode & 0xe003) == 0x2000) ||
>> -                    ((opcode & 0xe003) == 0x2002) ||
>> -                    ((opcode & 0xe003) == 0xa000) ||
>> -                    ((opcode & 0xe003) == 0xa002))) {
>> -            gen_exception_illegal(ctx);
> It's probably best to never add this in the first place.
>
> Remember that the extension can't be enabled until the last patch, so
> it's ok if we don't support it all in one go
>
> Alistair

OK.  I'll update it in next version.

Regards,

Weiwei Li

>
>>           } else {
>>               ctx->opcode = opcode;
>>               ctx->pc_succ_insn = ctx->base.pc_next + 2;
>> --
>> 2.25.1
>>
>>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 347bc913eb..a55b4a7849 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1087,13 +1087,6 @@  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
              ((opcode & 0xe003) == 0xe000) ||
              ((opcode & 0xe003) == 0xe002))) {
             gen_exception_illegal(ctx);
-        } else if (!(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zcd ||
-                     ctx->cfg_ptr->ext_zcmp || ctx->cfg_ptr->ext_zcmt) &&
-                   (((opcode & 0xe003) == 0x2000) ||
-                    ((opcode & 0xe003) == 0x2002) ||
-                    ((opcode & 0xe003) == 0xa000) ||
-                    ((opcode & 0xe003) == 0xa002))) {
-            gen_exception_illegal(ctx);
         } else {
             ctx->opcode = opcode;
             ctx->pc_succ_insn = ctx->base.pc_next + 2;