diff mbox series

[3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

Message ID 20221021213948.516041-4-anusha.srivatsa@intel.com (mailing list archive)
State New, archived
Headers show
Series Prep series - CDCLK code churn | expand

Commit Message

Srivatsa, Anusha Oct. 21, 2022, 9:39 p.m. UTC 
No functional change. Moving segments out to simplify
bxt_set_cdlck()

v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++++--------
 1 file changed, 25 insertions(+), 15 deletions(-)

Comments

Vivekanandan, Balasubramani Oct. 25, 2022, 5:43 p.m. UTC | #1 
On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Moving segments out to simplify
> bxt_set_cdlck()
> 
> v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++++--------
>  1 file changed, 25 insertions(+), 15 deletions(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 45babbc6290f..3893779e0c23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
>  	return 0xffff;
>  }
>  
> +static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> +	if (i915->display.cdclk.hw.vco != 0 &&
> +	    i915->display.cdclk.hw.vco != vco)
> +		icl_cdclk_pll_disable(i915);
> +
> +	if (i915->display.cdclk.hw.vco != vco)
> +		icl_cdclk_pll_enable(i915, vco);
> +}
> +
> +static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> +	if (i915->display.cdclk.hw.vco != 0 &&
> +	    i915->display.cdclk.hw.vco != vco)
> +		bxt_de_pll_disable(i915);
> +
> +	if (i915->display.cdclk.hw.vco != vco)
> +		bxt_de_pll_enable(i915, vco);
> +
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
>  		if (dev_priv->display.cdclk.hw.vco != vco)
>  			adlp_cdclk_pll_crawl(dev_priv, vco);
> -	} else if (DISPLAY_VER(dev_priv) >= 11) {
> -		if (dev_priv->display.cdclk.hw.vco != 0 &&
> -		    dev_priv->display.cdclk.hw.vco != vco)
> -			icl_cdclk_pll_disable(dev_priv);
> -
> -		if (dev_priv->display.cdclk.hw.vco != vco)
> -			icl_cdclk_pll_enable(dev_priv, vco);
> -	} else {
> -		if (dev_priv->display.cdclk.hw.vco != 0 &&
> -		    dev_priv->display.cdclk.hw.vco != vco)
> -			bxt_de_pll_disable(dev_priv);
> -
> -		if (dev_priv->display.cdclk.hw.vco != vco)
> -			bxt_de_pll_enable(dev_priv, vco);
> -	}
> +	} else if (DISPLAY_VER(dev_priv) >= 11)
> +		icl_cdclk_pll_update(dev_priv, vco);
> +	else
> +		bxt_cdclk_pll_update(dev_priv, vco);
>  
>  	waveform = cdclk_squash_waveform(dev_priv, cdclk);
>  
> -- 
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45babbc6290f..3893779e0c23 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1684,6 +1684,27 @@  static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
 	return 0xffff;
 }
 
+static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+	if (i915->display.cdclk.hw.vco != 0 &&
+	    i915->display.cdclk.hw.vco != vco)
+		icl_cdclk_pll_disable(i915);
+
+	if (i915->display.cdclk.hw.vco != vco)
+		icl_cdclk_pll_enable(i915, vco);
+}
+
+static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+	if (i915->display.cdclk.hw.vco != 0 &&
+	    i915->display.cdclk.hw.vco != vco)
+		bxt_de_pll_disable(i915);
+
+	if (i915->display.cdclk.hw.vco != vco)
+		bxt_de_pll_enable(i915, vco);
+
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1719,21 +1740,10 @@  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
 		if (dev_priv->display.cdclk.hw.vco != vco)
 			adlp_cdclk_pll_crawl(dev_priv, vco);
-	} else if (DISPLAY_VER(dev_priv) >= 11) {
-		if (dev_priv->display.cdclk.hw.vco != 0 &&
-		    dev_priv->display.cdclk.hw.vco != vco)
-			icl_cdclk_pll_disable(dev_priv);
-
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			icl_cdclk_pll_enable(dev_priv, vco);
-	} else {
-		if (dev_priv->display.cdclk.hw.vco != 0 &&
-		    dev_priv->display.cdclk.hw.vco != vco)
-			bxt_de_pll_disable(dev_priv);
-
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			bxt_de_pll_enable(dev_priv, vco);
-	}
+	} else if (DISPLAY_VER(dev_priv) >= 11)
+		icl_cdclk_pll_update(dev_priv, vco);
+	else
+		bxt_cdclk_pll_update(dev_priv, vco);
 
 	waveform = cdclk_squash_waveform(dev_priv, cdclk);