| Message ID | 20221024193647.1089769-1-conor@kernel.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [RFC] riscv: dts: microchip: add OPPs to mpfs | expand |
Hi Conor, > On Mon, 2022-10-24 at 20:36 +0100, Conor Dooley wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > The U-Boot dts for mpfs defines three OPPs which are missing from the > Linux dts. For ease of synchronisation of the two, add the missing > OPPs > to the Linux dt too. > > CC: Padmarao Begari <padmarao.begari@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > > Hey Padmarao, > I've been trying to pick off the bits that're different between the > Linux > & U-Boot dts. Do you remember why we added OPPs to the U-Boot dts but > didn't propagate them elsewhere? > Initially We added OPPs to the Linux dts for the CPU Frequency and Voltage scaling while bringing up the Linux on an Emulation Platform and the Icicle Kit for PolarFire SoC and same dts used for the U-Boot but the U-Boot dts upstreamed first. Regards Padmarao > arch/riscv/boot/dts/microchip/mpfs.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi > b/arch/riscv/boot/dts/microchip/mpfs.dtsi > index 0a9bb84af438..9d9ff7174341 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -23,6 +23,7 @@ cpu0: cpu@0 { > reg = <0>; > riscv,isa = "rv64imac"; > clocks = <&clkcfg CLK_CPU>; > + operating-points-v2 = <&cluster0_opps>; > status = "disabled"; > > cpu0_intc: interrupt-controller { > @@ -51,6 +52,7 @@ cpu1: cpu@1 { > clocks = <&clkcfg CLK_CPU>; > tlb-split; > next-level-cache = <&cctrllr>; > + operating-points-v2 = <&cluster0_opps>; > status = "okay"; > > cpu1_intc: interrupt-controller { > @@ -79,6 +81,7 @@ cpu2: cpu@2 { > clocks = <&clkcfg CLK_CPU>; > tlb-split; > next-level-cache = <&cctrllr>; > + operating-points-v2 = <&cluster0_opps>; > status = "okay"; > > cpu2_intc: interrupt-controller { > @@ -107,6 +110,7 @@ cpu3: cpu@3 { > clocks = <&clkcfg CLK_CPU>; > tlb-split; > next-level-cache = <&cctrllr>; > + operating-points-v2 = <&cluster0_opps>; > status = "okay"; > > cpu3_intc: interrupt-controller { > @@ -136,6 +140,7 @@ cpu4: cpu@4 { > tlb-split; > next-level-cache = <&cctrllr>; > status = "okay"; > + operating-points-v2 = <&cluster0_opps>; > cpu4_intc: interrupt-controller { > #interrupt-cells = <1>; > compatible = "riscv,cpu-intc"; > @@ -166,6 +171,24 @@ core4 { > }; > }; > }; > + > + cluster0_opps: opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-microvolt = <1100000>; > + }; > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + opp-microvolt = <950000>; > + }; > + opp-150000000 { > + opp-hz = /bits/ 64 <150000000>; > + opp-microvolt = <750000>; > + }; > + }; > }; > > refclk: mssrefclk { > -- > 2.38.0 >
On Wed, Oct 26, 2022 at 05:54:16AM +0000, Padmarao.Begari@microchip.com wrote: > Hi Conor, > > On Mon, 2022-10-24 at 20:36 +0100, Conor Dooley wrote: > > > > From: Conor Dooley <conor.dooley@microchip.com> > > > > The U-Boot dts for mpfs defines three OPPs which are missing from the > > Linux dts. For ease of synchronisation of the two, add the missing > > OPPs > > to the Linux dt too. > > > > CC: Padmarao Begari <padmarao.begari@microchip.com> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > > > Hey Padmarao, > > I've been trying to pick off the bits that're different between the > > Linux > > & U-Boot dts. Do you remember why we added OPPs to the U-Boot dts but > > didn't propagate them elsewhere? > > > > Initially We added OPPs to the Linux dts for the CPU Frequency and > Voltage scaling while bringing up the Linux on an Emulation Platform > and the Icicle Kit for PolarFire SoC and same dts used for the U-Boot > but the U-Boot dts upstreamed first. Right. So do we know if they're even correct values for an actual PolarFire SoC? > > arch/riscv/boot/dts/microchip/mpfs.dtsi | 23 +++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi > > b/arch/riscv/boot/dts/microchip/mpfs.dtsi > > index 0a9bb84af438..9d9ff7174341 100644 > > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > > @@ -23,6 +23,7 @@ cpu0: cpu@0 { > > reg = <0>; > > riscv,isa = "rv64imac"; > > clocks = <&clkcfg CLK_CPU>; > > + operating-points-v2 = <&cluster0_opps>; > > status = "disabled"; > > > > cpu0_intc: interrupt-controller { > > @@ -51,6 +52,7 @@ cpu1: cpu@1 { > > clocks = <&clkcfg CLK_CPU>; > > tlb-split; > > next-level-cache = <&cctrllr>; > > + operating-points-v2 = <&cluster0_opps>; > > status = "okay"; > > > > cpu1_intc: interrupt-controller { > > @@ -79,6 +81,7 @@ cpu2: cpu@2 { > > clocks = <&clkcfg CLK_CPU>; > > tlb-split; > > next-level-cache = <&cctrllr>; > > + operating-points-v2 = <&cluster0_opps>; > > status = "okay"; > > > > cpu2_intc: interrupt-controller { > > @@ -107,6 +110,7 @@ cpu3: cpu@3 { > > clocks = <&clkcfg CLK_CPU>; > > tlb-split; > > next-level-cache = <&cctrllr>; > > + operating-points-v2 = <&cluster0_opps>; > > status = "okay"; > > > > cpu3_intc: interrupt-controller { > > @@ -136,6 +140,7 @@ cpu4: cpu@4 { > > tlb-split; > > next-level-cache = <&cctrllr>; > > status = "okay"; > > + operating-points-v2 = <&cluster0_opps>; > > cpu4_intc: interrupt-controller { > > #interrupt-cells = <1>; > > compatible = "riscv,cpu-intc"; > > @@ -166,6 +171,24 @@ core4 { > > }; > > }; > > }; > > + > > + cluster0_opps: opp-table { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-600000000 { > > + opp-hz = /bits/ 64 <600000000>; > > + opp-microvolt = <1100000>; > > + }; > > + opp-300000000 { > > + opp-hz = /bits/ 64 <300000000>; > > + opp-microvolt = <950000>; > > + }; > > + opp-150000000 { > > + opp-hz = /bits/ 64 <150000000>; > > + opp-microvolt = <750000>; > > + }; > > + }; > > }; > > > > refclk: mssrefclk { > > -- > > 2.38.0 > >
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 0a9bb84af438..9d9ff7174341 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -23,6 +23,7 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; clocks = <&clkcfg CLK_CPU>; + operating-points-v2 = <&cluster0_opps>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -51,6 +52,7 @@ cpu1: cpu@1 { clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; + operating-points-v2 = <&cluster0_opps>; status = "okay"; cpu1_intc: interrupt-controller { @@ -79,6 +81,7 @@ cpu2: cpu@2 { clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; + operating-points-v2 = <&cluster0_opps>; status = "okay"; cpu2_intc: interrupt-controller { @@ -107,6 +110,7 @@ cpu3: cpu@3 { clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; + operating-points-v2 = <&cluster0_opps>; status = "okay"; cpu3_intc: interrupt-controller { @@ -136,6 +140,7 @@ cpu4: cpu@4 { tlb-split; next-level-cache = <&cctrllr>; status = "okay"; + operating-points-v2 = <&cluster0_opps>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -166,6 +171,24 @@ core4 { }; }; }; + + cluster0_opps: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <750000>; + }; + }; }; refclk: mssrefclk {