| Message ID | 20221027123432.1818530-5-robert.foss@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v1,1/5] clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350 | expand |
On 27/10/2022 15:34, Robert Foss wrote: > SM8150 does not have any of the link_div_clk_src clocks, so > let's disable them for this SoC. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8250.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > index d2aaa44ed3d4..f6f719616f63 100644 > --- a/drivers/clk/qcom/dispcc-sm8250.c > +++ b/drivers/clk/qcom/dispcc-sm8250.c > @@ -1289,6 +1289,10 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; > + > + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL; > + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL; > + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL; We also have to fix link_intf clocks: disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_dp_link_clk_src.clkr.hw; disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_dp_link1_clk_src.clkr.hw; disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] = &disp_cc_mdss_edp_link_clk_src.clkr.hw; > } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { > static struct clk_rcg2 * const rcgs[] = { > &disp_cc_mdss_byte0_clk_src,
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index d2aaa44ed3d4..f6f719616f63 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1289,6 +1289,10 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL; } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { static struct clk_rcg2 * const rcgs[] = { &disp_cc_mdss_byte0_clk_src,
SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 4 ++++ 1 file changed, 4 insertions(+)