| Message ID | 20221013183854.21087-9-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | Enhancements to pcie-tegra194 driver | expand |
On 14-10-22, 00:08, Vidya Sagar wrote: > Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change > to Gen1 during initialization. This helps in the below surprise link down > cases, > - Surprise link down happens at Gen3/Gen4 link speed. > - Surprise link down happens and external REFCLK is cut off, which causes > UPHY PLL rate to deviate to an invalid rate. This looks okay to me and I can go ahead and apply, PCI patches can come thru PCI tree and whenever ready use .calibrate() ? > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > V3: > * Removed "Reported-by: kernel test robot <lkp@intel.com>" based on Bjorn's review comment > * Reworded the commit message > > V2: > * Addressed review comment from test bot and Vinod > > drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c > index 1415ca71de38..633e6b747275 100644 > --- a/drivers/phy/tegra/phy-tegra194-p2u.c > +++ b/drivers/phy/tegra/phy-tegra194-p2u.c > @@ -15,6 +15,7 @@ > #include <linux/phy/phy.h> > > #define P2U_CONTROL_CMN 0x74 > +#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13) > #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) > > #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 > @@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x) > return 0; > } > > +static int tegra_p2u_calibrate(struct phy *x) > +{ > + struct tegra_p2u *phy = phy_get_drvdata(x); > + u32 val; > + > + val = p2u_readl(phy, P2U_CONTROL_CMN); > + val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE; > + p2u_writel(phy, val, P2U_CONTROL_CMN); > + > + return 0; > +} > + > static const struct phy_ops ops = { > .power_on = tegra_p2u_power_on, > + .calibrate = tegra_p2u_calibrate, > .owner = THIS_MODULE, > }; > > -- > 2.17.1
Thanks for the review and yes please go ahead and apply. Thanks, Vidya Sagar On 10/28/2022 5:12 PM, Vinod Koul wrote: > External email: Use caution opening links or attachments > > > On 14-10-22, 00:08, Vidya Sagar wrote: >> Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change >> to Gen1 during initialization. This helps in the below surprise link down >> cases, >> - Surprise link down happens at Gen3/Gen4 link speed. >> - Surprise link down happens and external REFCLK is cut off, which causes >> UPHY PLL rate to deviate to an invalid rate. > > This looks okay to me and I can go ahead and apply, PCI patches can come > thru PCI tree and whenever ready use .calibrate() ? > >> >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >> --- >> V3: >> * Removed "Reported-by: kernel test robot <lkp@intel.com>" based on Bjorn's review comment >> * Reworded the commit message >> >> V2: >> * Addressed review comment from test bot and Vinod >> >> drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c >> index 1415ca71de38..633e6b747275 100644 >> --- a/drivers/phy/tegra/phy-tegra194-p2u.c >> +++ b/drivers/phy/tegra/phy-tegra194-p2u.c >> @@ -15,6 +15,7 @@ >> #include <linux/phy/phy.h> >> >> #define P2U_CONTROL_CMN 0x74 >> +#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13) >> #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) >> >> #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 >> @@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x) >> return 0; >> } >> >> +static int tegra_p2u_calibrate(struct phy *x) >> +{ >> + struct tegra_p2u *phy = phy_get_drvdata(x); >> + u32 val; >> + >> + val = p2u_readl(phy, P2U_CONTROL_CMN); >> + val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE; >> + p2u_writel(phy, val, P2U_CONTROL_CMN); >> + >> + return 0; >> +} >> + >> static const struct phy_ops ops = { >> .power_on = tegra_p2u_power_on, >> + .calibrate = tegra_p2u_calibrate, >> .owner = THIS_MODULE, >> }; >> >> -- >> 2.17.1 > > -- > ~Vinod >
On 14-10-22, 00:08, Vidya Sagar wrote: > Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change > to Gen1 during initialization. This helps in the below surprise link down > cases, > - Surprise link down happens at Gen3/Gen4 link speed. > - Surprise link down happens and external REFCLK is cut off, which causes > UPHY PLL rate to deviate to an invalid rate. Applied, thanks
diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c index 1415ca71de38..633e6b747275 100644 --- a/drivers/phy/tegra/phy-tegra194-p2u.c +++ b/drivers/phy/tegra/phy-tegra194-p2u.c @@ -15,6 +15,7 @@ #include <linux/phy/phy.h> #define P2U_CONTROL_CMN 0x74 +#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13) #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 @@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x) return 0; } +static int tegra_p2u_calibrate(struct phy *x) +{ + struct tegra_p2u *phy = phy_get_drvdata(x); + u32 val; + + val = p2u_readl(phy, P2U_CONTROL_CMN); + val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE; + p2u_writel(phy, val, P2U_CONTROL_CMN); + + return 0; +} + static const struct phy_ops ops = { .power_on = tegra_p2u_power_on, + .calibrate = tegra_p2u_calibrate, .owner = THIS_MODULE, };
Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change to Gen1 during initialization. This helps in the below surprise link down cases, - Surprise link down happens at Gen3/Gen4 link speed. - Surprise link down happens and external REFCLK is cut off, which causes UPHY PLL rate to deviate to an invalid rate. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V3: * Removed "Reported-by: kernel test robot <lkp@intel.com>" based on Bjorn's review comment * Reworded the commit message V2: * Addressed review comment from test bot and Vinod drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)