| Message ID | 20221029020030.13936-2-jiaxun.yang@flygoat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MIPS system emulation miscellaneous fixes | expand |
On 29/10/22 04:00, Jiaxun Yang wrote: > As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX} > should is not writeable and hardcoded to 1. > > Without those bits set, kernel is unable to access XKPHYS address > segmant. So just set them up on CPU reset. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > target/mips/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > index d0a76b95f7..a870901bfa 100644 > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev) > env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? > 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; > env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); > + if (env->insn_flags & INSN_LOONGSON2F) { > + /* Loongson-2F has those bits hardcoded to 1 */ > + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | > + (1 << CP0St_UX); > + } Don't we want to update CP0_Status_rw_bitmask in Loongson-2F entry in mips_defs[] instead?
> 2022年10月29日 18:44，Philippe Mathieu-Daudé <philmd@linaro.org> 写道： > > On 29/10/22 04:00, Jiaxun Yang wrote: >> As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX} >> should is not writeable and hardcoded to 1. >> Without those bits set, kernel is unable to access XKPHYS address >> segmant. So just set them up on CPU reset. >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> --- >> target/mips/cpu.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >> index d0a76b95f7..a870901bfa 100644 >> --- a/target/mips/cpu.c >> +++ b/target/mips/cpu.c >> @@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev) >> env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? >> 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; >> env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); >> + if (env->insn_flags & INSN_LOONGSON2F) { >> + /* Loongson-2F has those bits hardcoded to 1 */ >> + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | >> + (1 << CP0St_UX); >> + } > > Don't we want to update CP0_Status_rw_bitmask in Loongson-2F > entry in mips_defs[] instead? Write to those bits is already disabled by CP0_Status_rw_bitmask. However real hardware had those bits set to 1 but QEMU default them to 0… Enable writing to those bits can also make kernel work but it mismatches actual hardware behavior. Thanks. --- Jiaxun Yang
On 29/10/22 21:50, Jiaxun Yang wrote: > > >> 2022年10月29日 18:44，Philippe Mathieu-Daudé <philmd@linaro.org> 写道： >> >> On 29/10/22 04:00, Jiaxun Yang wrote: >>> As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX} >>> should is not writeable and hardcoded to 1. >>> Without those bits set, kernel is unable to access XKPHYS address >>> segmant. So just set them up on CPU reset. >>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >>> --- >>> target/mips/cpu.c | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >>> index d0a76b95f7..a870901bfa 100644 >>> --- a/target/mips/cpu.c >>> +++ b/target/mips/cpu.c >>> @@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev) >>> env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? >>> 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; >>> env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); >>> + if (env->insn_flags & INSN_LOONGSON2F) { >>> + /* Loongson-2F has those bits hardcoded to 1 */ >>> + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | >>> + (1 << CP0St_UX); >>> + } >> >> Don't we want to update CP0_Status_rw_bitmask in Loongson-2F >> entry in mips_defs[] instead? > > Write to those bits is already disabled by CP0_Status_rw_bitmask. However real hardware > had those bits set to 1 but QEMU default them to 0… > > Enable writing to those bits can also make kernel work but it mismatches actual hardware > behavior. On "龙芯 2F 处理器用户手册 (0.1 版, 2007 年 8 月 )" Section 5.10 Status 寄存器(12) (page 57), CP0_Status bits 5..7 are 0. Can you share your "Loongson-2F processor user manual" doc?
> 2022年10月30日 00:19，Philippe Mathieu-Daudé <philmd@linaro.org> 写道： > > On 29/10/22 21:50, Jiaxun Yang wrote: >>> 2022年10月29日 18:44，Philippe Mathieu-Daudé <philmd@linaro.org> 写道： >>> >>> On 29/10/22 04:00, Jiaxun Yang wrote: >>>> As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX} >>>> should is not writeable and hardcoded to 1. >>>> Without those bits set, kernel is unable to access XKPHYS address >>>> segmant. So just set them up on CPU reset. >>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >>>> --- >>>> target/mips/cpu.c | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >>>> index d0a76b95f7..a870901bfa 100644 >>>> --- a/target/mips/cpu.c >>>> +++ b/target/mips/cpu.c >>>> @@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev) >>>> env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? >>>> 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; >>>> env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); >>>> + if (env->insn_flags & INSN_LOONGSON2F) { >>>> + /* Loongson-2F has those bits hardcoded to 1 */ >>>> + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | >>>> + (1 << CP0St_UX); >>>> + } >>> >>> Don't we want to update CP0_Status_rw_bitmask in Loongson-2F >>> entry in mips_defs[] instead? >> Write to those bits is already disabled by CP0_Status_rw_bitmask. However real hardware >> had those bits set to 1 but QEMU default them to 0… >> Enable writing to those bits can also make kernel work but it mismatches actual hardware >> behavior. > > On "龙芯 2F 处理器用户手册 (0.1 版, 2007 年 8 月)" > Section 5.10 Status 寄存器(12) (page 57), > CP0_Status bits 5..7 are 0. > > Can you share your "Loongson-2F processor user manual" doc? Ah sorry the document was marked as “company confidential” so I’m not sure if I can share the whole doc. It was updated in 2016 with version 1.8. The latest document I can find in wild Is version 1.5 [1] but it didn’t cover newer chip reversions. There is a footnote saying value of those bits was changed in later chips, to translate it says: "Since LS2F04 those bits was refined to 1. As in LS2F we had implemented a single 64 bit addressing model and it is mostly compatible with MIPS64 64 bit addressing model.” It is obvious that without KX and UX bit 64 bit kernel won’t work but my Lemote Fuloong box is running 64 bit kernel along with n64 AOSC/Retro [2] user-space rootfs. For SX bit as LS2F supports XSSEG it should work as well, though nobody take MIPS supervisor mode serious :-) [1]: https://github.com/loongson-community/docs/tree/master/2F [2]: https://wiki.aosc.io/aosc-os/retro/intro/ --- Jiaxun Yang
On 10/29/22 13:00, Jiaxun Yang wrote: > As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX} > should is not writeable and hardcoded to 1. > > Without those bits set, kernel is unable to access XKPHYS address > segmant. So just set them up on CPU reset. > > Signed-off-by: Jiaxun Yang<jiaxun.yang@flygoat.com> > --- > target/mips/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) Based on down-thread discussion of the manual: Acked-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a76b95f7..a870901bfa 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev) env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + if (env->insn_flags & INSN_LOONGSON2F) { + /* Loongson-2F has those bits hardcoded to 1 */ + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | + (1 << CP0St_UX); + } + /* * Vectored interrupts not implemented, timer on int 7, * no performance counters.
As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX} should is not writeable and hardcoded to 1. Without those bits set, kernel is unable to access XKPHYS address segmant. So just set them up on CPU reset. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- target/mips/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)