| Message ID | 20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Hi All, > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > entry-class social infrastructure gateway control and industrial gateway > control. > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - CPG > - PINCTRL Hey, Looks like you've got a pair of warnings here from dtbs_check. I tested this on top of 20221028's next, with the three branches below merged in, hopefully my merges aren't the source of them: linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml With this sorted, whatever wasn't already is now: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks for putting up with my messing around re: kconfig symbols and I am glad that we ended up being able to share the dts across archs in the end, so thanks to everyone involved in that :) > - PLIC > - SCIF0 > - SYSC > > Useful links: > ------------- > [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ > > Patch series depends on the below patches (which are queued in the Renesas tree for v6.2): > ------------------------------------------------------------------------------------ > [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55 > [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e > [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0 > [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835 > > v4 -> v5: > --------- > * Rebased patches on -next > * Included RB tags > * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees > * Patch #7 from v4 was not needed anymore so dropped it > * Patches #4 and #5 are new > > v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > Below are the logs from RZ/Five SMARC EVK: > ------------------------------------------ > > / # uname -ra; > Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux > / # cat /proc/cpuinfo; > processor : 0 > hart : 0 > isa : rv64imafdc > mmu : sv39 > uarch : andestech,ax45mp > mvendorid : 0x31e > marchid : 0x8000000000008a45 > mimpid : 0x500 > > / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/ > soc0/$i; done > machine: Renesas SMARC EVK based on r9a07g043f01 > family: RZ/Five > soc_id: r9a07g043 > revision: 0 > / # > / # cat /proc/interrupts > CPU0 > 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err > 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full > 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty > 4: 0 SiFive PLIC 413 Level 1004b800.serial:break > 5: 41826 RISC-V INTC 5 Edge riscv-timer > 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready > IPI0: 0 Rescheduling interrupts > IPI1: 0 Function call interrupts > IPI2: 0 CPU stop interrupts > IPI3: 0 IRQ work interrupts > IPI4: 0 Timer broadcast interrupts > / # > / # cat /proc/meminfo > MemTotal: 882252 kB > MemFree: 860848 kB > MemAvailable: 858608 kB > Buffers: 0 kB > Cached: 1796 kB > SwapCached: 0 kB > Active: 0 kB > Inactive: 72 kB > Active(anon): 0 kB > Inactive(anon): 72 kB > Active(file): 0 kB > Inactive(file): 0 kB > Unevictable: 1796 kB > Mlocked: 0 kB > SwapTotal: 0 kB > SwapFree: 0 kB > Dirty: 0 kB > Writeback: 0 kB > AnonPages: 108 kB > Mapped: 1200 kB > Shmem: 0 kB > KReclaimable: 6760 kB > Slab: 12360 kB > SReclaimable: 6760 kB > SUnreclaim: 5600 kB > KernelStack: 620 kB > PageTables: 32 kB > SecPageTables: 0 kB > NFS_Unstable: 0 kB > Bounce: 0 kB > WritebackTmp: 0 kB > CommitLimit: 441124 kB > Committed_AS: 592 kB > VmallocTotal: 67108864 kB > VmallocUsed: 1132 kB > VmallocChunk: 0 kB > Percpu: 84 kB > HugePages_Total: 0 > HugePages_Free: 0 > HugePages_Rsvd: 0 > HugePages_Surp: 0 > Hugepagesize: 2048 kB > Hugetlb: 0 kB > / # > / # > > Cheers, > Prabhakar > > Lad Prabhakar (7): > dt-bindings: riscv: Sort the CPU core list alphabetically > dt-bindings: riscv: Add Andes AX45MP core to the list > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK > MAINTAINERS: Add entry for Renesas RISC-V > riscv: configs: defconfig: Enable Renesas RZ/Five SoC > > .../devicetree/bindings/riscv/cpus.yaml | 11 ++- > MAINTAINERS | 3 +- > arch/riscv/Kconfig.socs | 5 + > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/renesas/Makefile | 2 + > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++ > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++ > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++ > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++ > arch/riscv/configs/defconfig | 3 + > 10 files changed, 252 insertions(+), 6 deletions(-) > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi > > -- > 2.25.1 >
Hi Conor, On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Hi All, > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > entry-class social infrastructure gateway control and industrial gateway > > control. > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > Hey, > Looks like you've got a pair of warnings here from dtbs_check. I tested > this on top of 20221028's next, with the three branches below merged in, > hopefully my merges aren't the source of them: > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > Thanks for the review and test. The warnings above are coming from [0] as support for IRQC is missing, once that is added the warnings should go away. > With this sorted, whatever wasn't already is now: > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Thanks for putting up with my messing around re: kconfig symbols and I > am glad that we ended up being able to share the dts across archs in the > end, so thanks to everyone involved in that :) > :-) [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi Cheers, Prabhakar
On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote: > Hi Conor, > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Hi All, > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > entry-class social infrastructure gateway control and industrial gateway > > > control. > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > > - AX45MP CPU > > > - CPG > > > - PINCTRL > > > > Hey, > > Looks like you've got a pair of warnings here from dtbs_check. I tested > > this on top of 20221028's next, with the three branches below merged in, > > hopefully my merges aren't the source of them: > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > Thanks for the review and test. The warnings above are coming from [0] > as support for IRQC is missing, once that is added the warnings should > go away. Right. I merged in the stuff in Geert's trees & I don't think I saw any pending patches in the cover that I missed. Is there something else that adds the support that's not going to make v6.2? I got rid of all the dtbs_check warnings for v6.1 and I'd really like to keep things that way! > > With this sorted, whatever wasn't already is now: > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Thanks for putting up with my messing around re: kconfig symbols and I > > am glad that we ended up being able to share the dts across archs in the > > end, so thanks to everyone involved in that :) > > > :-) > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > Cheers, > Prabhakar
Hi Conor, On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote: > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote: > > Hi Conor, > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Hi All, > > > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > > entry-class social infrastructure gateway control and industrial gateway > > > > control. > > > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > - AX45MP CPU > > > > - CPG > > > > - PINCTRL > > > > > > Hey, > > > Looks like you've got a pair of warnings here from dtbs_check. I tested > > > this on top of 20221028's next, with the three branches below merged in, > > > hopefully my merges aren't the source of them: > > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > Thanks for the review and test. The warnings above are coming from [0] > > as support for IRQC is missing, once that is added the warnings should > > go away. > > Right. I merged in the stuff in Geert's trees & I don't think I saw any > pending patches in the cover that I missed. Is there something else that > adds the support that's not going to make v6.2? I got rid of all the > dtbs_check warnings for v6.1 and I'd really like to keep things that > way! > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the cover letter. I'll make sure I get it posted asap and merged for v6.2. Cheers, Prabhakar
Hi Conor, On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Conor, > > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote: > > > Hi Conor, > > > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > > > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Hi All, > > > > > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > > > entry-class social infrastructure gateway control and industrial gateway > > > > > control. > > > > > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > - AX45MP CPU > > > > > - CPG > > > > > - PINCTRL > > > > > > > > Hey, > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested > > > > this on top of 20221028's next, with the three branches below merged in, > > > > hopefully my merges aren't the source of them: > > > > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > > > Thanks for the review and test. The warnings above are coming from [0] > > > as support for IRQC is missing, once that is added the warnings should > > > go away. > > > > Right. I merged in the stuff in Geert's trees & I don't think I saw any > > pending patches in the cover that I missed. Is there something else that > > adds the support that's not going to make v6.2? I got rid of all the > > dtbs_check warnings for v6.1 and I'd really like to keep things that > > way! > > > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the > cover letter. I'll make sure I get it posted asap and merged for v6.2. > I have got the patches out [0] which will fix the warnings seen above. BTW on the riscv patchwork I see status as fail "Patch does not apply to for-next" does that mean I need to resend re-basing on your tree? [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar
On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote: > Hi Conor, > > On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > > > Hi Conor, > > > > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote: > > > > > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote: > > > > Hi Conor, > > > > > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > > > > > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Hi All, > > > > > > > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > > > > entry-class social infrastructure gateway control and industrial gateway > > > > > > control. > > > > > > > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > > - AX45MP CPU > > > > > > - CPG > > > > > > - PINCTRL > > > > > > > > > > Hey, > > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested > > > > > this on top of 20221028's next, with the three branches below merged in, > > > > > hopefully my merges aren't the source of them: > > > > > > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > > > > > Thanks for the review and test. The warnings above are coming from [0] > > > > as support for IRQC is missing, once that is added the warnings should > > > > go away. > > > > > > Right. I merged in the stuff in Geert's trees & I don't think I saw any > > > pending patches in the cover that I missed. Is there something else that > > > adds the support that's not going to make v6.2? I got rid of all the > > > dtbs_check warnings for v6.1 and I'd really like to keep things that > > > way! > > > > > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the > > cover letter. I'll make sure I get it posted asap and merged for v6.2. > > > I have got the patches out [0] which will fix the warnings seen above. Cool, thanks :) > > BTW on the riscv patchwork I see status as fail "Patch does not apply > to for-next" does that mean I need to resend re-basing on your tree? Nah, I though that Geert would be applying this patchset, no? If that's the case, it only needs to apply to his tree. Geert, are you waiting for an ack from Palmer? > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > Cheers, > Prabhakar
Hi Conor, On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote: > On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote: > > On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar > > <prabhakar.csengg@gmail.com> wrote: > > > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote: > > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > > > > > > entry-class social infrastructure gateway control and industrial gateway > > > > > > > control. > > > > > > > > > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > > > - AX45MP CPU > > > > > > > - CPG > > > > > > > - PINCTRL > > > > > > > > > > > > Hey, > > > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested > > > > > > this on top of 20221028's next, with the three branches below merged in, > > > > > > hopefully my merges aren't the source of them: > > > > > > > > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > > > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > > > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > > > > > > > > > > > Thanks for the review and test. The warnings above are coming from [0] > > > > > as support for IRQC is missing, once that is added the warnings should > > > > > go away. > > > > > > > > Right. I merged in the stuff in Geert's trees & I don't think I saw any > > > > pending patches in the cover that I missed. Is there something else that > > > > adds the support that's not going to make v6.2? I got rid of all the > > > > dtbs_check warnings for v6.1 and I'd really like to keep things that > > > > way! > > > > > > > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the > > > cover letter. I'll make sure I get it posted asap and merged for v6.2. > > BTW on the riscv patchwork I see status as fail "Patch does not apply > > to for-next" does that mean I need to resend re-basing on your tree? > > Nah, I though that Geert would be applying this patchset, no? > If that's the case, it only needs to apply to his tree. > > Geert, are you waiting for an ack from Palmer? I can take: - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V (4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel them to the SoC-people. I can take - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC with an ack from Palmer. The rest - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list should probably go through the riscv tree, to avoid merge conflicts when support for other SoCs is added? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Tue, Nov 08, 2022 at 05:02:57PM +0100, Geert Uytterhoeven wrote: > Hi Conor, > On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote: > > Geert, are you waiting for an ack from Palmer? > > I can take: > - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for > Renesas RZ/Five SoC > - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas > RZ/Five SMARC EVK > - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V > (4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel > them to the SoC-people. > > I can take > - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option > - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC > with an ack from Palmer. > > The rest > - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically > - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list > should probably go through the riscv tree, to avoid merge conflicts > when support for other SoCs is added? Or depending on the outcome of [0], maybe I take the dt-binding stuff? Either way, looks like an ack from Palmer is needed for 3 & 7. I can do the video call version of a ping on that tomorrow at the pw sync thing. [0] - https://lore.kernel.org/linux-riscv/Y2puchRvbo6+YJSy@wendy/T/#me49f1e779dee210d3ab6fc4bc308dbaed036e1a8
On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Hi All, > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > entry-class social infrastructure gateway control and industrial gateway > control. > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - CPG > - PINCTRL > - PLIC > - SCIF0 > - SYSC > > Useful links: > ------------- > [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ > > Patch series depends on the below patches (which are queued in the Renesas tree for v6.2): > ------------------------------------------------------------------------------------ > [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55 > [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e > [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0 > [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835 > > v4 -> v5: > --------- > * Rebased patches on -next > * Included RB tags > * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees > * Patch #7 from v4 was not needed anymore so dropped it > * Patches #4 and #5 are new > > v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > Below are the logs from RZ/Five SMARC EVK: > ------------------------------------------ > > / # uname -ra; > Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux > / # cat /proc/cpuinfo; > processor : 0 > hart : 0 > isa : rv64imafdc > mmu : sv39 > uarch : andestech,ax45mp > mvendorid : 0x31e > marchid : 0x8000000000008a45 > mimpid : 0x500 > > / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/ > soc0/$i; done > machine: Renesas SMARC EVK based on r9a07g043f01 > family: RZ/Five > soc_id: r9a07g043 > revision: 0 > / # > / # cat /proc/interrupts > CPU0 > 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err > 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full > 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty > 4: 0 SiFive PLIC 413 Level 1004b800.serial:break > 5: 41826 RISC-V INTC 5 Edge riscv-timer > 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready > IPI0: 0 Rescheduling interrupts > IPI1: 0 Function call interrupts > IPI2: 0 CPU stop interrupts > IPI3: 0 IRQ work interrupts > IPI4: 0 Timer broadcast interrupts > / # > / # cat /proc/meminfo > MemTotal: 882252 kB > MemFree: 860848 kB > MemAvailable: 858608 kB > Buffers: 0 kB > Cached: 1796 kB > SwapCached: 0 kB > Active: 0 kB > Inactive: 72 kB > Active(anon): 0 kB > Inactive(anon): 72 kB > Active(file): 0 kB > Inactive(file): 0 kB > Unevictable: 1796 kB > Mlocked: 0 kB > SwapTotal: 0 kB > SwapFree: 0 kB > Dirty: 0 kB > Writeback: 0 kB > AnonPages: 108 kB > Mapped: 1200 kB > Shmem: 0 kB > KReclaimable: 6760 kB > Slab: 12360 kB > SReclaimable: 6760 kB > SUnreclaim: 5600 kB > KernelStack: 620 kB > PageTables: 32 kB > SecPageTables: 0 kB > NFS_Unstable: 0 kB > Bounce: 0 kB > WritebackTmp: 0 kB > CommitLimit: 441124 kB > Committed_AS: 592 kB > VmallocTotal: 67108864 kB > VmallocUsed: 1132 kB > VmallocChunk: 0 kB > Percpu: 84 kB > HugePages_Total: 0 > HugePages_Free: 0 > HugePages_Rsvd: 0 > HugePages_Surp: 0 > Hugepagesize: 2048 kB > Hugetlb: 0 kB > / # > / # > > Cheers, > Prabhakar > > Lad Prabhakar (7): > dt-bindings: riscv: Sort the CPU core list alphabetically > dt-bindings: riscv: Add Andes AX45MP core to the list > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK > MAINTAINERS: Add entry for Renesas RISC-V > riscv: configs: defconfig: Enable Renesas RZ/Five SoC > > .../devicetree/bindings/riscv/cpus.yaml | 11 ++- > MAINTAINERS | 3 +- > arch/riscv/Kconfig.socs | 5 + > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/renesas/Makefile | 2 + > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++ > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++ > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++ > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++ > arch/riscv/configs/defconfig | 3 + > 10 files changed, 252 insertions(+), 6 deletions(-) > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi Geert was mentioning taking these though one of his trees, that works for me so Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Happy to do a shared tag or whatever, but I think we can just skip that here. The only conflicts would be defconfig and Kconfig.socs, but I don't think anything big is in the works for either -- unless Conor was planning on re-spinning that Kconfig.socs rework? Thanks!
On Wed, Nov 09, 2022 at 11:55:24AM -0800, Palmer Dabbelt wrote: > On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Lad Prabhakar (7): > > dt-bindings: riscv: Sort the CPU core list alphabetically > > dt-bindings: riscv: Add Andes AX45MP core to the list > > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option > > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC > > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK > > MAINTAINERS: Add entry for Renesas RISC-V > > riscv: configs: defconfig: Enable Renesas RZ/Five SoC > Geert was mentioning taking these though one of his trees, that works for me > so > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Happy to do a shared tag or whatever, but I think we can just skip that > here. The only conflicts would be defconfig and Kconfig.socs, but I don't > think anything big is in the works for either -- unless Conor was planning > on re-spinning that Kconfig.socs rework? Uh, nah. I've got a wee bit (the removal of selects) that is "ready" but there's zero urgency so it can wait for after v6.2-rc1. I don't think it'd conflict anyway. The rest of it I need to sort out a v1 of, but I've been distracted. Should be safe to take the defconfig & Kconfig.socs stuff in terms of me doing anything. Geert, would you be able to apply the first two patches on top of v6.1-rc1 just in case, as you mentioned previously, it needs to become part of a shared branch? Seems unlikely at this point in the cycle though. Thanks, Conor.
Hi Conor, On Wed, Nov 9, 2022 at 10:21 PM Conor Dooley <conor@kernel.org> wrote: > On Wed, Nov 09, 2022 at 11:55:24AM -0800, Palmer Dabbelt wrote: > > On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote: > > > Lad Prabhakar (7): > > > dt-bindings: riscv: Sort the CPU core list alphabetically > > > dt-bindings: riscv: Add Andes AX45MP core to the list > > > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option > > > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC > > > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK > > > MAINTAINERS: Add entry for Renesas RISC-V > > > riscv: configs: defconfig: Enable Renesas RZ/Five SoC > > > Geert was mentioning taking these though one of his trees, that works for me > > so > > > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Series queued in renesas-devel for v6.2, spread across a few existing and new branches to be pulled by soc, taking into account dependencies. > > Happy to do a shared tag or whatever, but I think we can just skip that > > here. The only conflicts would be defconfig and Kconfig.socs, but I don't > > think anything big is in the works for either -- unless Conor was planning > > on re-spinning that Kconfig.socs rework? > > Uh, nah. I've got a wee bit (the removal of selects) that is "ready" but > there's zero urgency so it can wait for after v6.2-rc1. I don't think > it'd conflict anyway. The rest of it I need to sort out a v1 of, but I've > been distracted. Should be safe to take the defconfig & Kconfig.socs stuff > in terms of me doing anything. > > Geert, would you be able to apply the first two patches on top of > v6.1-rc1 just in case, as you mentioned previously, it needs to become > part of a shared branch? Seems unlikely at this point in the cycle > though. The bindings are in the existing renesas-dt-bindings-for-v6.2 branch, which is based on v6.1-rc1, and only had RZ/Five related commits anyway. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as entry-class social infrastructure gateway control and industrial gateway control. This patch series adds initial SoC DTSi support for Renesas RZ/Five (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - CPG - PINCTRL - PLIC - SCIF0 - SYSC Useful links: ------------- [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Patch series depends on the below patches (which are queued in the Renesas tree for v6.2): ------------------------------------------------------------------------------------ [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55 [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108 [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0 [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835 v4 -> v5: --------- * Rebased patches on -next * Included RB tags * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees * Patch #7 from v4 was not needed anymore so dropped it * Patches #4 and #5 are new v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Below are the logs from RZ/Five SMARC EVK: ------------------------------------------ / # uname -ra; Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux / # cat /proc/cpuinfo; processor : 0 hart : 0 isa : rv64imafdc mmu : sv39 uarch : andestech,ax45mp mvendorid : 0x31e marchid : 0x8000000000008a45 mimpid : 0x500 / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/ soc0/$i; done machine: Renesas SMARC EVK based on r9a07g043f01 family: RZ/Five soc_id: r9a07g043 revision: 0 / # / # cat /proc/interrupts CPU0 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty 4: 0 SiFive PLIC 413 Level 1004b800.serial:break 5: 41826 RISC-V INTC 5 Edge riscv-timer 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready IPI0: 0 Rescheduling interrupts IPI1: 0 Function call interrupts IPI2: 0 CPU stop interrupts IPI3: 0 IRQ work interrupts IPI4: 0 Timer broadcast interrupts / # / # cat /proc/meminfo MemTotal: 882252 kB MemFree: 860848 kB MemAvailable: 858608 kB Buffers: 0 kB Cached: 1796 kB SwapCached: 0 kB Active: 0 kB Inactive: 72 kB Active(anon): 0 kB Inactive(anon): 72 kB Active(file): 0 kB Inactive(file): 0 kB Unevictable: 1796 kB Mlocked: 0 kB SwapTotal: 0 kB SwapFree: 0 kB Dirty: 0 kB Writeback: 0 kB AnonPages: 108 kB Mapped: 1200 kB Shmem: 0 kB KReclaimable: 6760 kB Slab: 12360 kB SReclaimable: 6760 kB SUnreclaim: 5600 kB KernelStack: 620 kB PageTables: 32 kB SecPageTables: 0 kB NFS_Unstable: 0 kB Bounce: 0 kB WritebackTmp: 0 kB CommitLimit: 441124 kB Committed_AS: 592 kB VmallocTotal: 67108864 kB VmallocUsed: 1132 kB VmallocChunk: 0 kB Percpu: 84 kB HugePages_Total: 0 HugePages_Free: 0 HugePages_Rsvd: 0 HugePages_Surp: 0 Hugepagesize: 2048 kB Hugetlb: 0 kB / # / # Cheers, Prabhakar Lad Prabhakar (7): dt-bindings: riscv: Sort the CPU core list alphabetically dt-bindings: riscv: Add Andes AX45MP core to the list riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK MAINTAINERS: Add entry for Renesas RISC-V riscv: configs: defconfig: Enable Renesas RZ/Five SoC .../devicetree/bindings/riscv/cpus.yaml | 11 ++- MAINTAINERS | 3 +- arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++ .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++ arch/riscv/configs/defconfig | 3 + 10 files changed, 252 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi