| Message ID | 20221031135416.350010-1-j-choudhary@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator | expand |
On Mon, Oct 31, 2022 at 07:24:16PM +0530, Jayesh Choudhary wrote: > Add the node for SA2UL for supporting hardware crypto algorithms, > including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites. > Add rng node for hardware random number generator. > > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Acked-by: Matt Ranostay <mranostay@ti.com> > --- > > Changes have been tested on local j721s2-evm board. Tcrypt tests > and crypto self-tests were passing. > > Changelog v1 -> v2: > - change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU > domain SA2UL instance and not the main domain instance > - remove the 'dma-coherent' property (Binding changes are merged) > - add the rng node which can be used as well for hwrng along with > optee-rng > > v1 patch: https://lore.kernel.org/all/20220628054518.350717-1-j-choudhary@ti.com/ > > Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8 > > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index d1ec26110376..7b828afc9280 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -72,6 +72,26 @@ main_pmx0: pinctrl@11c000 { > pinctrl-single,function-mask = <0xffffffff>; > }; > > + main_crypto: crypto@4e00000 { > + compatible = "ti,j721e-sa2ul"; > + reg = <0x00 0x4e00000 0x00 0x1200>; > + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; > + > + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, > + <&main_udmap 0x4a41>; > + dma-names = "tx", "rx1", "rx2"; > + > + rng: rng@4e10000 { > + compatible = "inside-secure,safexcel-eip76"; > + reg = <0x0 0x4e10000 0x0 0x7d>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&k3_clks 297 1>; > + }; > + }; > + > main_uart0: serial@2800000 { > compatible = "ti,j721e-uart", "ti,am654-uart"; > reg = <0x00 0x02800000 0x00 0x200>; > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 10/31/22 8:54 AM, Jayesh Choudhary wrote: > Add the node for SA2UL for supporting hardware crypto algorithms, > including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites. > Add rng node for hardware random number generator. > > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> > --- > > Changes have been tested on local j721s2-evm board. Tcrypt tests > and crypto self-tests were passing. > > Changelog v1 -> v2: > - change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU > domain SA2UL instance and not the main domain instance > - remove the 'dma-coherent' property (Binding changes are merged) > - add the rng node which can be used as well for hwrng along with > optee-rng > > v1 patch: https://lore.kernel.org/all/20220628054518.350717-1-j-choudhary@ti.com/ > > Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8 > > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index d1ec26110376..7b828afc9280 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -72,6 +72,26 @@ main_pmx0: pinctrl@11c000 { > pinctrl-single,function-mask = <0xffffffff>; > }; > > + main_crypto: crypto@4e00000 { > + compatible = "ti,j721e-sa2ul"; > + reg = <0x00 0x4e00000 0x00 0x1200>; > + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; > + > + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, > + <&main_udmap 0x4a41>; > + dma-names = "tx", "rx1", "rx2"; > + > + rng: rng@4e10000 { > + compatible = "inside-secure,safexcel-eip76"; > + reg = <0x0 0x4e10000 0x0 0x7d>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&k3_clks 297 1>; This "clocks" property can be dropped now [0]. Otherwise, LGTM Acked-by: Andrew Davis <afd@ti.com> [0] d7e8c41016471 dt-bindings: rng: omap_rng: Drop requirement for clocks > + }; > + }; > + > main_uart0: serial@2800000 { > compatible = "ti,j721e-uart", "ti,am654-uart"; > reg = <0x00 0x02800000 0x00 0x200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index d1ec26110376..7b828afc9280 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -72,6 +72,26 @@ main_pmx0: pinctrl@11c000 { pinctrl-single,function-mask = <0xffffffff>; }; + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x4e00000 0x00 0x1200>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x0 0x4e10000 0x0 0x7d>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 297 1>; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>;
Add the node for SA2UL for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> --- Changes have been tested on local j721s2-evm board. Tcrypt tests and crypto self-tests were passing. Changelog v1 -> v2: - change the TI_SCI flag from shared to exclusive as OP-TEE uses MCU domain SA2UL instance and not the main domain instance - remove the 'dma-coherent' property (Binding changes are merged) - add the rng node which can be used as well for hwrng along with optee-rng v1 patch: https://lore.kernel.org/all/20220628054518.350717-1-j-choudhary@ti.com/ Testing log: https://gist.github.com/Jayesh2000/26acf0e63f7edcd4b267122e4c73b9a8 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)