| Message ID | 20221102174544.2288205-3-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSC slice/PSR2 SU panel y granularity alignment | expand |
On Wed, 2022-11-02 at 19:45 +0200, Jouni Högander wrote: > Selective update area is now aligned with DSC slice height when > DSC is enabled. Remove inappropriate warning about missing DSC > alignment. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Mika Kahola <mika.kahola@intel.com> > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 57575b5c6d48..a75b37851504 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1684,9 +1684,6 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c > pipe_clip->y1 -= pipe_clip->y1 % y_alignment; > if (pipe_clip->y2 % y_alignment) > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; > - > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) > - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); > } > > /*
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 57575b5c6d48..a75b37851504 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1684,9 +1684,6 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c pipe_clip->y1 -= pipe_clip->y1 % y_alignment; if (pipe_clip->y2 % y_alignment) pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; - - if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); } /*
Selective update area is now aligned with DSC slice height when DSC is enabled. Remove inappropriate warning about missing DSC alignment. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-)