diff mbox series

dt-bindings: cpufreq: qcom: Add missing cache related properties

Message ID 20221104162429.1981729-1-robh@kernel.org (mailing list archive)
State New, archived
Delegated to: viresh kumar
Headers show
Series dt-bindings: cpufreq: qcom: Add missing cache related properties | expand

Commit Message

Rob Herring (Arm) Nov. 4, 2022, 4:24 p.m. UTC 
The examples' cache nodes are incomplete as 'cache-unified' and
'cache-level' are required cache properties.

Signed-off-by: Rob Herring <robh@kernel.org>
---
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

Krzysztof Kozlowski Nov. 6, 2022, 10:31 a.m. UTC | #1 
On 04/11/2022 17:24, Rob Herring wrote:
> The examples' cache nodes are incomplete as 'cache-unified' and
> 'cache-level' are required cache properties.
> 
> Signed-off-by: Rob Herring <robh@kernel.org>



Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Viresh Kumar Nov. 7, 2022, 5:49 a.m. UTC | #2 
On 04-11-22, 11:24, Rob Herring wrote:
> The examples' cache nodes are incomplete as 'cache-unified' and
> 'cache-level' are required cache properties.
> 
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml      | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)

Applied. Thanks.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 24fa3d87a40b..e58c55f78aaa 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -85,9 +85,13 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 0>;
         L2_0: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
           L3_0: l3-cache {
             compatible = "cache";
+            cache-unified;
+            cache-level = <3>;
           };
         };
       };
@@ -101,6 +105,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 0>;
         L2_100: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };
@@ -114,6 +120,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 0>;
         L2_200: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };
@@ -127,6 +135,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 0>;
         L2_300: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };
@@ -140,6 +150,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 1>;
         L2_400: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };
@@ -153,6 +165,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 1>;
         L2_500: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };
@@ -166,6 +180,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 1>;
         L2_600: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };
@@ -179,6 +195,8 @@  examples:
         qcom,freq-domain = <&cpufreq_hw 1>;
         L2_700: l2-cache {
           compatible = "cache";
+          cache-unified;
+          cache-level = <2>;
           next-level-cache = <&L3_0>;
         };
       };