| Message ID | 20221031092115.533560-1-pierre.gondois@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update cache properties for arm64 DTS | expand |
On Mon, Oct 31, 2022 at 10:21:14AM +0100, Pierre Gondois wrote: > The DeviceTree Specification v0.3 specifies that the cache node > 'compatible' and 'cache-level' properties are 'required'. Cf. > s3.8 Multi-level and Shared Cache Nodes > > The recently added init_of_cache_level() function checks > these properties. Add them if missing. > > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi > index 0949acee4728..926da7e1a6ba 100644 > --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi > +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi > @@ -64,6 +64,7 @@ cpu3: cpu@3 { > > l2: cache { > compatible = "cache"; > + cache-level = <2>; > }; > > idle-states { > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 0949acee4728..926da7e1a6ba 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -64,6 +64,7 @@ cpu3: cpu@3 { l2: cache { compatible = "cache"; + cache-level = <2>; }; idle-states {
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> --- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 + 1 file changed, 1 insertion(+)