| Message ID | 20221113023251.11047-3-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support subsets of code size reduction extension | expand |
On 11/13/22 12:32, Weiwei Li wrote: > + } else if ((get_xl_max(ctx) == MXL_RV32) && > + !ctx->cfg_ptr->ext_zcf && > + (((opcode & 0xe003) == 0x6000) || > + ((opcode & 0xe003) == 0x6002) || > + ((opcode & 0xe003) == 0xe000) || > + ((opcode & 0xe003) == 0xe002))) { > gen_exception_illegal(ctx); Why aren't you using the same c_flw solution that you do for Zcd? r~
On 2022/11/14 05:40, Richard Henderson wrote: > On 11/13/22 12:32, Weiwei Li wrote: >> + } else if ((get_xl_max(ctx) == MXL_RV32) && >> + !ctx->cfg_ptr->ext_zcf && >> + (((opcode & 0xe003) == 0x6000) || >> + ((opcode & 0xe003) == 0x6002) || >> + ((opcode & 0xe003) == 0xe000) || >> + ((opcode & 0xe003) == 0xe002))) { >> gen_exception_illegal(ctx); > > Why aren't you using the same c_flw solution that you do for Zcd? Yeah, it's OK for zcf intructions to use the c_flw solution. I tried to remain the original logic for Zcf and Zcd instructions, However, this way is not suitable for Zcd instructions since zcmp/zcmt instructions will overlap their encodings(but not the same). So I changed the way of Zcd instructions. Regards, Weiwei Li > > > r~
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 5c69b88d1e..0d73b919ce 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); gen_set_pc(ctx, cpu_pc); - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { TCGv t0 = tcg_temp_new(); misaligned = gen_new_label(); @@ -178,7 +178,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) gen_set_label(l); /* branch taken */ - if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { + if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2ab8772ebe..0514e43fd3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -557,7 +557,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) /* check misaligned: */ next_pc = ctx->base.pc_next + imm; - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { if ((next_pc & 0x3) != 0) { gen_exception_inst_addr_mis(ctx); return; @@ -1097,7 +1097,19 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) ctx->virt_inst_excp = false; /* Check for compressed insn */ if (insn_len(opcode) == 2) { - if (!has_ext(ctx, RVC)) { + /* + * Zca support all of the existing C extension, excluding all + * compressed floating point loads and stores + * Zcf(RV32 only) support c.flw, c.flwsp, c.fsw, c.fswsp + */ + if (!ctx->cfg_ptr->ext_zca) { + gen_exception_illegal(ctx); + } else if ((get_xl_max(ctx) == MXL_RV32) && + !ctx->cfg_ptr->ext_zcf && + (((opcode & 0xe003) == 0x6000) || + ((opcode & 0xe003) == 0x6002) || + ((opcode & 0xe003) == 0xe000) || + ((opcode & 0xe003) == 0xe002))) { gen_exception_illegal(ctx); } else { ctx->opcode = opcode;