mbox series

[GIT,PULL,0/7] Renesas SoC updates for v6.2 (take two)

Message ID cover.1668788918.git.geert+renesas@glider.be (mailing list archive)
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Series Renesas SoC updates for v6.2 (take two) | expand

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Geert Uytterhoeven Nov. 18, 2022, 4:44 p.m. UTC
Hi SoC folks,

This is my second pull request for the inclusion of Renesas SoC updates
for v6.2, and the first one including support for an SoC with a RISC-V
CPU core (and including no changes for SoCs with arm32 CPU cores).

It consists of 7 parts:

  [GIT PULL 1/7] Renesas ARM defconfig updates for v6.2

    - Enable support for Renesas R-Car S4-8 Spider Ethernet devices in the
      arm64 defconfig.

  [GIT PULL 2/7] Renesas ARM DT updates for v6.2 (take two)

    - Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for
      the R-Car V4H SoC,
    - Watchdog, L2 cache, and system controller support for the RZ/V2M
      SoC on the RZ/V2M Evaluation Kit 2.0,
    - Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the
      Spider development board,
    - Miscellaneous fixes and improvements.

  [GIT PULL 3/7] Renesas driver updates for v6.2 (take two)

    - Add support for identifying the SoC revision on RZ/V2M.

  [GIT PULL 4/7] Renesas DT binding updates for v6.2 (take two)

    - Document support for the Andes Technology AX45MP RISC-V CPU Core, as
      used on the Renesas RZ/Five SoC,
    - Document support for the Renesas RZ/V2M System Configuration.

  [GIT PULL 5/7] Renesas RISC-V defconfig updates for v6.2

    - Enable support for the Renesas RZ/Five SoC and the RZ/Five SMARC EVK
      board in the risc-v defconfig.

  [GIT PULL 6/7] Renesas RISC-V DT updates for v6.2

    - Add initial support for the Renesas RZ/Five SoC and the Renesas
      RZ/Five SMARC EVK development board.

  [GIT PULL 7/7] Renesas RISC-V SoC updates for v6.2

    - Add Kconfig option for Renesas RISC-V SoCs.

Thanks for pulling!

P.S. I'm wondering if I should reduce the number of branches?
     Probably it would make sense to (at least) use a single branch for
     the DTS changes, as the RZ/Five DTS files share base SoC and board
     DTS with RZ/G2UL through #include <arm64/renesas/...>.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Comments

patchwork-bot+linux-soc@kernel.org Nov. 21, 2022, 2:52 p.m. UTC | #1
Hello:

This series was applied to soc/soc.git (for-next)
by Arnd Bergmann <arnd@arndb.de>:

On Fri, 18 Nov 2022 17:44:57 +0100 you wrote:
> Hi SoC folks,
> 
> This is my second pull request for the inclusion of Renesas SoC updates
> for v6.2, and the first one including support for an SoC with a RISC-V
> CPU core (and including no changes for SoCs with arm32 CPU cores).
> 
> It consists of 7 parts:
> 
> [...]

Here is the summary with links:
  - [GIT,PULL,1/7] Renesas ARM defconfig updates for v6.2
    https://git.kernel.org/soc/soc/c/1d4456221fe3
  - [GIT,PULL,2/7] Renesas ARM DT updates for v6.2 (take two)
    https://git.kernel.org/soc/soc/c/1e9629820ab3
  - [GIT,PULL,3/7] Renesas driver updates for v6.2 (take two)
    https://git.kernel.org/soc/soc/c/cb667ad7524a
  - [GIT,PULL,4/7] Renesas DT binding updates for v6.2 (take two)
    https://git.kernel.org/soc/soc/c/f241625bb3ae
  - [GIT,PULL,5/7] Renesas RISC-V defconfig updates for v6.2
    https://git.kernel.org/soc/soc/c/267511c9778b
  - [GIT,PULL,6/7] Renesas RISC-V DT updates for v6.2
    https://git.kernel.org/soc/soc/c/2092ad3a79ca
  - [GIT,PULL,7/7] Renesas RISC-V SoC updates for v6.2
    https://git.kernel.org/soc/soc/c/92f3bfaced6e

You are awesome, thank you!