diff mbox series

[v2] clk: qcom: ipq8074: populate fw_name for all parents

Message ID 20221116214655.1116467-1-robimarko@gmail.com (mailing list archive)
State Accepted
Commit 35dc8e101a8e08f69f4725839b98ec0f11a8e2d3
Headers show
Series [v2] clk: qcom: ipq8074: populate fw_name for all parents | expand

Commit Message

Robert Marko Nov. 16, 2022, 9:46 p.m. UTC 
It appears that having only .name populated in parent_data for clocks
which are only globally searchable currently will not work as the clk core
won't copy that name if there is no .fw_name present as well.

So, populate .fw_name for all parent clocks in parent_data.

Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")

Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v2:
* Add fw_name for PCIe PHY pipe clocks as well
---
 drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
 1 file changed, 26 insertions(+), 26 deletions(-)

Comments

Stephen Boyd Nov. 23, 2022, 2:30 a.m. UTC | #1 
Quoting Robert Marko (2022-11-16 13:46:55)
> It appears that having only .name populated in parent_data for clocks
> which are only globally searchable currently will not work as the clk core
> won't copy that name if there is no .fw_name present as well.
> 
> So, populate .fw_name for all parent clocks in parent_data.
> 
> Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
> 
> Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
> Changes in v2:
> * Add fw_name for PCIe PHY pipe clocks as well
> ---
>  drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
>  1 file changed, 26 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
> index d231866804f6..8374cc40915a 100644
> --- a/drivers/clk/qcom/gcc-ipq8074.c
> +++ b/drivers/clk/qcom/gcc-ipq8074.c
> @@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src = {
>  };
>  
>  static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
> -       { .name = "pcie20_phy0_pipe_clk" },
> +       { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },

Is there a DT binding update for these firmware names?
Robert Marko Nov. 23, 2022, 9:24 a.m. UTC | #2 
On Wed, 23 Nov 2022 at 03:30, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Robert Marko (2022-11-16 13:46:55)
> > It appears that having only .name populated in parent_data for clocks
> > which are only globally searchable currently will not work as the clk core
> > won't copy that name if there is no .fw_name present as well.
> >
> > So, populate .fw_name for all parent clocks in parent_data.
> >
> > Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
> >
> > Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > ---
> > Changes in v2:
> > * Add fw_name for PCIe PHY pipe clocks as well
> > ---
> >  drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
> >  1 file changed, 26 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
> > index d231866804f6..8374cc40915a 100644
> > --- a/drivers/clk/qcom/gcc-ipq8074.c
> > +++ b/drivers/clk/qcom/gcc-ipq8074.c
> > @@ -680,7 +680,7 @@ static struct clk_rcg2 pcie0_aux_clk_src = {
> >  };
> >
> >  static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
> > -       { .name = "pcie20_phy0_pipe_clk" },
> > +       { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
>
> Is there a DT binding update for these firmware names?

Hi Stephen,
I have that name documented as part of series for passing the QMP
PCI output clock directly to GCC instead of global matching that
I wanted to send after this and PCI fixups were merged.

I can change it to match the global name, but that is a bit confusing
as pcie20_phy0_pipe_clk is actually from the Gen3 PHY but the GCC
driver was made for v1 of the SoC which was pre-production and then
it got updated to support v2 which is only supported so the name stuck
as it would break backwards compatibility.

Regards,
Robert
Bjorn Andersson Dec. 2, 2022, 8:58 p.m. UTC | #3 
On Wed, 16 Nov 2022 22:46:55 +0100, Robert Marko wrote:
> It appears that having only .name populated in parent_data for clocks
> which are only globally searchable currently will not work as the clk core
> won't copy that name if there is no .fw_name present as well.
> 
> So, populate .fw_name for all parent clocks in parent_data.
> 
> Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: ipq8074: populate fw_name for all parents
      commit: 35dc8e101a8e08f69f4725839b98ec0f11a8e2d3

Best regards,
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index d231866804f6..8374cc40915a 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -680,7 +680,7 @@  static struct clk_rcg2 pcie0_aux_clk_src = {
 };
 
 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
-	{ .name = "pcie20_phy0_pipe_clk" },
+	{ .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
 	{ .fw_name = "xo", .name = "xo" },
 };
 
@@ -733,7 +733,7 @@  static struct clk_rcg2 pcie1_aux_clk_src = {
 };
 
 static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
-	{ .name = "pcie20_phy1_pipe_clk" },
+	{ .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
 	{ .fw_name = "xo", .name = "xo" },
 };
 
@@ -1137,7 +1137,7 @@  static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "bias_pll_nss_noc_clk" },
+	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll2.clkr.hw },
 };
@@ -1362,7 +1362,7 @@  static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll4.clkr.hw },
 	{ .hw = &nss_crypto_pll.clkr.hw },
@@ -1413,10 +1413,10 @@  static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "uniphy0_gcc_rx_clk" },
-	{ .name = "uniphy0_gcc_tx_clk" },
+	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -1465,10 +1465,10 @@  static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "uniphy0_gcc_tx_clk" },
-	{ .name = "uniphy0_gcc_rx_clk" },
+	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1696,12 +1696,12 @@  static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "uniphy0_gcc_rx_clk" },
-	{ .name = "uniphy0_gcc_tx_clk" },
-	{ .name = "uniphy1_gcc_rx_clk" },
-	{ .name = "uniphy1_gcc_tx_clk" },
+	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map
@@ -1758,12 +1758,12 @@  static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "uniphy0_gcc_tx_clk" },
-	{ .name = "uniphy0_gcc_rx_clk" },
-	{ .name = "uniphy1_gcc_tx_clk" },
-	{ .name = "uniphy1_gcc_rx_clk" },
+	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map
@@ -1820,10 +1820,10 @@  static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "uniphy2_gcc_rx_clk" },
-	{ .name = "uniphy2_gcc_tx_clk" },
+	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
+	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
@@ -1877,10 +1877,10 @@  static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
 
 static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
 	{ .fw_name = "xo", .name = "xo" },
-	{ .name = "uniphy2_gcc_tx_clk" },
-	{ .name = "uniphy2_gcc_rx_clk" },
+	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
+	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
 	{ .hw = &ubi32_pll.clkr.hw },
-	{ .name = "bias_pll_cc_clk" },
+	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
 };
 
 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {