| Message ID | 20221110150035.2824580-5-adeep@lexina.in (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: amlogic: mmc: meson-gx: Add core, tx, rx | expand |
Hi Vyacheslav, On Thu, Nov 10, 2022 at 4:01 PM Vyacheslav Bocharov <adeep@lexina.in> wrote: [...] > +- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values: > + 0: CLK_PHASE_0 - 0 phase > + 1: CLK_PHASE_90 - 90 phase > + 2: CLK_PHASE_180 - 180 phase > + 3: CLK_PHASE_270 - 270 phase As mentioned in another patch: I'd go with the human readable values (0, 90, 180, 270) instead of the register bits. [...] > + amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>; Also I *think* the format here is not correct, for an array of three u32 values this should be: amlogic,mmc-phases = <CLK_PHASE_180>, <CLK_PHASE_0>, <CLK_PHASE_0>; Best regards, Martin
On 10/11/2022 16:00, Vyacheslav Bocharov wrote: > - amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx Use subject prefixes matching the subsystem (git log --oneline -- ...). > clock with values: > 0: CLK_PHASE_0 - 0 phase > 1: CLK_PHASE_90 - 90 phase > 2: CLK_PHASE_180 - 180 phase > 3: CLK_PHASE_270 - 270 phase > By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value. Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. You missed several people. > > Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in> > > diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt > index ccc5358db131..98c89c5b3455 100644 > --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt > +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt > @@ -25,6 +25,12 @@ Required properties: > Optional properties: > - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the > DRAM memory, like on the G12A dedicated SDIO controller. > +- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values: > + 0: CLK_PHASE_0 - 0 phase > + 1: CLK_PHASE_90 - 90 phase > + 2: CLK_PHASE_180 - 180 phase > + 3: CLK_PHASE_270 - 270 phase > + By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value. No, this has to be converted to DT schema first. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt index ccc5358db131..98c89c5b3455 100644 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt @@ -25,6 +25,12 @@ Required properties: Optional properties: - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the DRAM memory, like on the G12A dedicated SDIO controller. +- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values: + 0: CLK_PHASE_0 - 0 phase + 1: CLK_PHASE_90 - 90 phase + 2: CLK_PHASE_180 - 180 phase + 3: CLK_PHASE_270 - 270 phase + By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value. Example: @@ -36,4 +42,5 @@ Example: clock-names = "core", "clkin0", "clkin1"; pinctrl-0 = <&emmc_pins>; resets = <&reset RESET_SD_EMMC_A>; + amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>; };
- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values: 0: CLK_PHASE_0 - 0 phase 1: CLK_PHASE_90 - 90 phase 2: CLK_PHASE_180 - 180 phase 3: CLK_PHASE_270 - 270 phase By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value. Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>