Message ID | 20221116135504.258687-7-daire.mcnamara@microchip.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Lorenzo Pieralisi |
Headers | show |
Series | PCI: microchip: Partition address translations | expand |
On Wed, Nov 16, 2022 at 01:55:01PM +0000, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > Continuing to use pci_host_common_probe() for the PCIe root complex on > PolarFire SoC was leading to an extremely large _init() function and > some unnatural code flow. Re-partition so some tasks are done in > a _probe() routine, which calls pci_host_common_probe() and then use a > much smaller _init() function, mainly to enable interrupts after address > translation tables are set up. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/pci/controller/pcie-microchip-host.c | 55 ++++++++++++++------ > 1 file changed, 38 insertions(+), 17 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index faecf419ad6f..73856647f321 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -381,6 +381,8 @@ static struct { > > static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; > > +static struct mc_pcie *port; > + > static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam) > { > struct mc_msi *msi = &port->msi; > @@ -1095,7 +1097,34 @@ static int mc_platform_init(struct pci_config_window *cfg) > { > struct device *dev = cfg->parent; > struct platform_device *pdev = to_platform_device(dev); > - struct mc_pcie *port; > + void __iomem *bridge_base_addr = > + port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > + int ret; > + > + /* Configure address translation table 0 for PCIe config space */ > + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, > + cfg->res.start, > + resource_size(&cfg->res)); > + > + /* Need some fixups in config space */ > + mc_pcie_fixup_ecam(port, cfg->win); > + > + /* Configure non-config space outbound ranges */ > + ret = mc_pcie_setup_windows(pdev, port); > + if (ret) > + return ret; > + > + /* address translation is up; safe to enable interrupts */ I think that Bjorn mentioned it elsewhere, but consistent capitalisation would be nice. Otherwise, code movement looks good to me. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > + ret = mc_init_interrupts(pdev, port); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int mc_host_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > void __iomem *bridge_base_addr; > void __iomem *ctrl_base_addr; > int ret; > @@ -1104,13 +1133,8 @@ static int mc_platform_init(struct pci_config_window *cfg) > port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); > if (!port) > return -ENOMEM; > - port->dev = dev; > > - ret = mc_pcie_init_clks(dev); > - if (ret) { > - dev_err(dev, "failed to get clock resources, error %d\n", ret); > - return -ENODEV; > - } > + port->dev = dev; > > port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); > if (IS_ERR(port->axi_base_addr)) > @@ -1136,16 +1160,13 @@ static int mc_platform_init(struct pci_config_window *cfg) > /* pick vector address from design */ > port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); > > - /* Configure Address Translation Table 0 for PCIe config space */ > - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, > - cfg->res.start, resource_size(&cfg->res)); > - > - ret = mc_pcie_setup_windows(pdev, port); > - if (ret) > - return ret; > + ret = mc_pcie_init_clks(dev); > + if (ret) { > + dev_err(dev, "failed to get clock resources, error %d\n", ret); > + return -ENODEV; > + } > > - /* address translation is up; safe to enable interrupts */ > - return mc_init_interrupts(pdev, port); > + return pci_host_common_probe(pdev); > } > > static const struct pci_ecam_ops mc_ecam_ops = { > @@ -1168,7 +1189,7 @@ static const struct of_device_id mc_pcie_of_match[] = { > MODULE_DEVICE_TABLE(of, mc_pcie_of_match); > > static struct platform_driver mc_pcie_driver = { > - .probe = pci_host_common_probe, > + .probe = mc_host_probe, > .driver = { > .name = "microchip-pcie", > .of_match_table = mc_pcie_of_match, > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index faecf419ad6f..73856647f321 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -381,6 +381,8 @@ static struct { static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; +static struct mc_pcie *port; + static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam) { struct mc_msi *msi = &port->msi; @@ -1095,7 +1097,34 @@ static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; struct platform_device *pdev = to_platform_device(dev); - struct mc_pcie *port; + void __iomem *bridge_base_addr = + port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + int ret; + + /* Configure address translation table 0 for PCIe config space */ + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, + cfg->res.start, + resource_size(&cfg->res)); + + /* Need some fixups in config space */ + mc_pcie_fixup_ecam(port, cfg->win); + + /* Configure non-config space outbound ranges */ + ret = mc_pcie_setup_windows(pdev, port); + if (ret) + return ret; + + /* address translation is up; safe to enable interrupts */ + ret = mc_init_interrupts(pdev, port); + if (ret) + return ret; + + return 0; +} + +static int mc_host_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; void __iomem *bridge_base_addr; void __iomem *ctrl_base_addr; int ret; @@ -1104,13 +1133,8 @@ static int mc_platform_init(struct pci_config_window *cfg) port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); if (!port) return -ENOMEM; - port->dev = dev; - ret = mc_pcie_init_clks(dev); - if (ret) { - dev_err(dev, "failed to get clock resources, error %d\n", ret); - return -ENODEV; - } + port->dev = dev; port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(port->axi_base_addr)) @@ -1136,16 +1160,13 @@ static int mc_platform_init(struct pci_config_window *cfg) /* pick vector address from design */ port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); - /* Configure Address Translation Table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, - cfg->res.start, resource_size(&cfg->res)); - - ret = mc_pcie_setup_windows(pdev, port); - if (ret) - return ret; + ret = mc_pcie_init_clks(dev); + if (ret) { + dev_err(dev, "failed to get clock resources, error %d\n", ret); + return -ENODEV; + } - /* address translation is up; safe to enable interrupts */ - return mc_init_interrupts(pdev, port); + return pci_host_common_probe(pdev); } static const struct pci_ecam_ops mc_ecam_ops = { @@ -1168,7 +1189,7 @@ static const struct of_device_id mc_pcie_of_match[] = { MODULE_DEVICE_TABLE(of, mc_pcie_of_match); static struct platform_driver mc_pcie_driver = { - .probe = pci_host_common_probe, + .probe = mc_host_probe, .driver = { .name = "microchip-pcie", .of_match_table = mc_pcie_of_match,