| Message ID | 20221126224740.311625-4-marex@denx.de (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells | expand |
> Subject: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data > in OCOTP > > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values in OCOTP. Add the OCOTP calibration values phandle so the > TMU driver can perform this programming. > > The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 > uses 4. > > Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> > --- > Cc: Adam Ford <aford173@gmail.com> > Cc: Alice Guo <alice.guo@nxp.com> > Cc: Amit Kucheria <amitk@kernel.org> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Li Jun <jun.li@nxp.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rafael J. Wysocki <rafael@kernel.org> > Cc: Richard Cochran <richardcochran@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Zhang Rui <rui.zhang@intel.com> > Cc: devicetree@vger.kernel.org > To: linux-pm@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ > 3 files changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 513c2de0caa15..0cd7fff47c44d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -496,6 +496,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MM_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* > 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 068f599cdf757..5eef9b274edde 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -498,6 +498,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mn-tmu", "fsl,imx8mm- > tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MN_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* > 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index ddcd5e23ba47d..0173e394ad4d8 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -380,6 +380,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mp-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk > IMX8MP_CLK_TSENSOR_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <1>; > }; > > @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ > eth_mac2: mac-address@96 { /* 0x658 */ > reg = <0x96 6>; > }; > + > + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ > + reg = <0x264 0x10>; > + }; > }; > > anatop: clock-controller@30360000 { > -- > 2.35.1
Hi Marek, Am Samstag, 26. November 2022, 23:47:39 CET schrieb Marek Vasut: > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values in OCOTP. Add the OCOTP calibration values phandle so > the TMU driver can perform this programming. > > The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. Is there any source for the fuse addresses? I can only find OCOTP_OCOTP_HW_OCOTP_ANA1 and a calibration description in TMU section in the IMX8MNRM Rev 2, but I can't find any fuse for imx8mm and imx8mp. Best regards, Alexander > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Adam Ford <aford173@gmail.com> > Cc: Alice Guo <alice.guo@nxp.com> > Cc: Amit Kucheria <amitk@kernel.org> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Li Jun <jun.li@nxp.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rafael J. Wysocki <rafael@kernel.org> > Cc: Richard Cochran <richardcochran@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Zhang Rui <rui.zhang@intel.com> > Cc: devicetree@vger.kernel.org > To: linux-pm@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ > 3 files changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index > 513c2de0caa15..0cd7fff47c44d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -496,6 +496,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MM_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index > 068f599cdf757..5eef9b274edde 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -498,6 +498,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MN_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > ddcd5e23ba47d..0173e394ad4d8 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -380,6 +380,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mp-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <1>; > }; > > @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ > eth_mac2: mac-address@96 { /* 0x658 */ > reg = <0x96 6>; > }; > + > + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ > + reg = <0x264 0x10>; > + }; > }; > > anatop: clock-controller@30360000 {
On 11/28/22 09:34, Alexander Stein wrote: > Hi Marek, Hi, > Am Samstag, 26. November 2022, 23:47:39 CET schrieb Marek Vasut: >> The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with >> calibration values in OCOTP. Add the OCOTP calibration values phandle so >> the TMU driver can perform this programming. >> >> The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. > > Is there any source for the fuse addresses? I can only find > OCOTP_OCOTP_HW_OCOTP_ANA1 and a calibration description in TMU section in the > IMX8MNRM Rev 2, but I can't find any fuse for imx8mm and imx8mp. See 5/5 in this series, the offsets are pulled from U-Boot. The documentation seems to be lacking in this case, I couldn't find anything there either.
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 513c2de0caa15..0cd7fff47c44d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -496,6 +496,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 068f599cdf757..5eef9b274edde 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -498,6 +498,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ddcd5e23ba47d..0173e394ad4d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -380,6 +380,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; }; @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; }; anatop: clock-controller@30360000 {
The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with calibration values in OCOTP. Add the OCOTP calibration values phandle so the TMU driver can perform this programming. The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Adam Ford <aford173@gmail.com> Cc: Alice Guo <alice.guo@nxp.com> Cc: Amit Kucheria <amitk@kernel.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Li Jun <jun.li@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Rafael J. Wysocki <rafael@kernel.org> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Zhang Rui <rui.zhang@intel.com> Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 3 files changed, 18 insertions(+)