| Message ID | 20221125105954.149267-1-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] riscv: Add RISCVCPUConfig.satp_mode to set sv48, sv57, etc. | expand |
On Fri, Nov 25, 2022 at 7:01 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode in the satp_mode property. And the bare mode is > always supported. > > You can set this new property as follows: > -cpu rv64,satp-mode=sv48 # Linux will boot using sv48 scheme > -cpu rv64,satp-mode=sv39 # Linux will boot using sv39 scheme > > In addition, we now correctly set the device-tree entry 'mmu-type' using > this new satp_mode property. > > Reviewed-by: Atish Patra <atishp@rivosinc.com> > Co-Developed-by: Ludovic Henry <ludovic@rivosinc.com> > Signed-off-by: Ludovic Henry <ludovic@rivosinc.com> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > > v2: > - Use error_setg + return as suggested by Alistair > - Add RB from Atish > - Fixed checkpatch issues missed in v1 > - Replaced Ludovic email address with the rivos one > > hw/riscv/virt.c | 15 ++++++--------- > target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 3 +++ > target/riscv/csr.c | 8 ++++++-- > 4 files changed, 60 insertions(+), 11 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index a5bc7353b4..77484b5cae 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -228,7 +228,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > - char *name, *cpu_name, *core_name, *intc_name; > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -236,14 +236,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > cpu_name = g_strdup_printf("/cpus/cpu@%d", > s->soc[socket].hartid_base + cpu); > qemu_fdt_add_subnode(mc->fdt, cpu_name); > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > - RISCV_FEATURE_MMU)) { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > - } else { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - "riscv,none"); > - } > + > + sv_name = g_strdup_printf("riscv,%s", > + s->soc[socket].harts[cpu].cfg.satp_mode_str); > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > + Missing sv_name free > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > g_free(name); > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d14e95c9dc..c86dc5058d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -907,6 +907,48 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + /* > + * Either a cpu sets its supported satp_mode in XXX_cpu_init > + * or the user sets this value using satp_mode property. > + */ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + if (cpu->cfg.satp_mode_str) { > + if (!g_strcmp0(cpu->cfg.satp_mode_str, "none")) > + cpu->cfg.satp_mode = VM_1_10_MBARE; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv32") && rv32) > + cpu->cfg.satp_mode = VM_1_10_SV32; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv39") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV39; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv48") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV48; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv57") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV57; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv64") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV64; > + else { > + error_setg(errp, "Unknown option for satp_mode: %s", > + cpu->cfg.satp_mode_str); > + return; > + } > + } else { > + /* > + * If unset by both the user and the cpu, we fallback to sv32 for 32-bit > + * or sv57 for 64-bit when a MMU is present, and bare otherwise. > + */ > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + if (rv32) { > + cpu->cfg.satp_mode_str = g_strdup("sv32"); > + cpu->cfg.satp_mode = VM_1_10_SV32; > + } else { > + cpu->cfg.satp_mode_str = g_strdup("sv57"); > + cpu->cfg.satp_mode = VM_1_10_SV57; > + } > + } else { > + cpu->cfg.satp_mode_str = g_strdup("none"); > + cpu->cfg.satp_mode = VM_1_10_MBARE; > + } > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -1094,6 +1136,9 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), > DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), > + > + DEFINE_PROP_STRING("satp-mode", RISCVCPU, cfg.satp_mode_str), > + > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3a9e25053f..a6c229470b 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -480,6 +480,9 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + uint8_t satp_mode; > + char *satp_mode_str; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5c9a7ee287..d2aab1627e 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1109,10 +1109,14 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static int validate_vm(CPURISCVState *env, target_ulong vm) > { > + vm &= 0xf; > + > if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > + return valid_vm_1_10_32[vm] && > + (vm <= RISCV_CPU(env_cpu(env))->cfg.satp_mode); > } else { > - return valid_vm_1_10_64[vm & 0xf]; > + return valid_vm_1_10_64[vm] && > + (vm <= RISCV_CPU(env_cpu(env))->cfg.satp_mode); > } > } Regards, Bin
On Fri, Nov 25, 2022 at 11:59:54AM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode in the satp_mode property. And the bare mode is > always supported. > > You can set this new property as follows: > -cpu rv64,satp-mode=sv48 # Linux will boot using sv48 scheme > -cpu rv64,satp-mode=sv39 # Linux will boot using sv39 scheme Hi Alexandre, Please define separate boolean properties for each supported mode, e.g. sv32, sv48, sv57. We should try to always use booleans for cpu feature properties, because cpu model expansion users would otherwise need to be taught legal values. In this case, libvirt would need to be taught these "sv*" strings and if more are added to qemu, then older libvirt will report errors for the new valid modes, as it wouldn't be aware of them. With booleans, libvirt old and new simply asks for each cpu model boolean property to probe what's available, and then it can try to enable and disable them to probe what can/cannot be enabled/disabled. See target/arm/monitor.c:qmp_query_cpu_model_expansion() for an example of cpu model expansion. We'll eventually want to write a function like that for riscv too. Also, as all smaller widths must be supported, then riscv_cpu_realize() should validate that nobody has done something like sv32=off,sv48=on. When we get a qmp_query_cpu_model_expansion() for riscv, this same validation will need to run, so it may be best to add a finalize function like arm's arm_cpu_finalize_features() now. Thanks, drew > > In addition, we now correctly set the device-tree entry 'mmu-type' using > this new satp_mode property. > > Reviewed-by: Atish Patra <atishp@rivosinc.com> > Co-Developed-by: Ludovic Henry <ludovic@rivosinc.com> > Signed-off-by: Ludovic Henry <ludovic@rivosinc.com> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > > v2: > - Use error_setg + return as suggested by Alistair > - Add RB from Atish > - Fixed checkpatch issues missed in v1 > - Replaced Ludovic email address with the rivos one > > hw/riscv/virt.c | 15 ++++++--------- > target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 3 +++ > target/riscv/csr.c | 8 ++++++-- > 4 files changed, 60 insertions(+), 11 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index a5bc7353b4..77484b5cae 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -228,7 +228,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > - char *name, *cpu_name, *core_name, *intc_name; > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -236,14 +236,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > cpu_name = g_strdup_printf("/cpus/cpu@%d", > s->soc[socket].hartid_base + cpu); > qemu_fdt_add_subnode(mc->fdt, cpu_name); > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > - RISCV_FEATURE_MMU)) { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > - } else { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - "riscv,none"); > - } > + > + sv_name = g_strdup_printf("riscv,%s", > + s->soc[socket].harts[cpu].cfg.satp_mode_str); > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > + > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > g_free(name); > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d14e95c9dc..c86dc5058d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -907,6 +907,48 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + /* > + * Either a cpu sets its supported satp_mode in XXX_cpu_init > + * or the user sets this value using satp_mode property. > + */ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + if (cpu->cfg.satp_mode_str) { > + if (!g_strcmp0(cpu->cfg.satp_mode_str, "none")) > + cpu->cfg.satp_mode = VM_1_10_MBARE; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv32") && rv32) > + cpu->cfg.satp_mode = VM_1_10_SV32; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv39") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV39; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv48") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV48; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv57") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV57; > + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv64") && !rv32) > + cpu->cfg.satp_mode = VM_1_10_SV64; > + else { > + error_setg(errp, "Unknown option for satp_mode: %s", > + cpu->cfg.satp_mode_str); > + return; > + } > + } else { > + /* > + * If unset by both the user and the cpu, we fallback to sv32 for 32-bit > + * or sv57 for 64-bit when a MMU is present, and bare otherwise. > + */ > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + if (rv32) { > + cpu->cfg.satp_mode_str = g_strdup("sv32"); > + cpu->cfg.satp_mode = VM_1_10_SV32; > + } else { > + cpu->cfg.satp_mode_str = g_strdup("sv57"); > + cpu->cfg.satp_mode = VM_1_10_SV57; > + } > + } else { > + cpu->cfg.satp_mode_str = g_strdup("none"); > + cpu->cfg.satp_mode = VM_1_10_MBARE; > + } > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -1094,6 +1136,9 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), > DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), > + > + DEFINE_PROP_STRING("satp-mode", RISCVCPU, cfg.satp_mode_str), > + > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3a9e25053f..a6c229470b 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -480,6 +480,9 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + uint8_t satp_mode; > + char *satp_mode_str; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5c9a7ee287..d2aab1627e 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1109,10 +1109,14 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static int validate_vm(CPURISCVState *env, target_ulong vm) > { > + vm &= 0xf; > + > if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > + return valid_vm_1_10_32[vm] && > + (vm <= RISCV_CPU(env_cpu(env))->cfg.satp_mode); > } else { > - return valid_vm_1_10_64[vm & 0xf]; > + return valid_vm_1_10_64[vm] && > + (vm <= RISCV_CPU(env_cpu(env))->cfg.satp_mode); > } > } > > -- > 2.37.2 > >
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a5bc7353b4..77484b5cae 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +236,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); - } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - "riscv,none"); - } + + sv_name = g_strdup_printf("riscv,%s", + s->soc[socket].harts[cpu].cfg.satp_mode_str); + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); + name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); g_free(name); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d14e95c9dc..c86dc5058d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -907,6 +907,48 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + /* + * Either a cpu sets its supported satp_mode in XXX_cpu_init + * or the user sets this value using satp_mode property. + */ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + if (cpu->cfg.satp_mode_str) { + if (!g_strcmp0(cpu->cfg.satp_mode_str, "none")) + cpu->cfg.satp_mode = VM_1_10_MBARE; + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv32") && rv32) + cpu->cfg.satp_mode = VM_1_10_SV32; + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv39") && !rv32) + cpu->cfg.satp_mode = VM_1_10_SV39; + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv48") && !rv32) + cpu->cfg.satp_mode = VM_1_10_SV48; + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv57") && !rv32) + cpu->cfg.satp_mode = VM_1_10_SV57; + else if (!g_strcmp0(cpu->cfg.satp_mode_str, "sv64") && !rv32) + cpu->cfg.satp_mode = VM_1_10_SV64; + else { + error_setg(errp, "Unknown option for satp_mode: %s", + cpu->cfg.satp_mode_str); + return; + } + } else { + /* + * If unset by both the user and the cpu, we fallback to sv32 for 32-bit + * or sv57 for 64-bit when a MMU is present, and bare otherwise. + */ + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + if (rv32) { + cpu->cfg.satp_mode_str = g_strdup("sv32"); + cpu->cfg.satp_mode = VM_1_10_SV32; + } else { + cpu->cfg.satp_mode_str = g_strdup("sv57"); + cpu->cfg.satp_mode = VM_1_10_SV57; + } + } else { + cpu->cfg.satp_mode_str = g_strdup("none"); + cpu->cfg.satp_mode = VM_1_10_MBARE; + } + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -1094,6 +1136,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), + + DEFINE_PROP_STRING("satp-mode", RISCVCPU, cfg.satp_mode_str), + DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3a9e25053f..a6c229470b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,9 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + + uint8_t satp_mode; + char *satp_mode_str; }; typedef struct RISCVCPUConfig RISCVCPUConfig; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c9a7ee287..d2aab1627e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1109,10 +1109,14 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static int validate_vm(CPURISCVState *env, target_ulong vm) { + vm &= 0xf; + if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; + return valid_vm_1_10_32[vm] && + (vm <= RISCV_CPU(env_cpu(env))->cfg.satp_mode); } else { - return valid_vm_1_10_64[vm & 0xf]; + return valid_vm_1_10_64[vm] && + (vm <= RISCV_CPU(env_cpu(env))->cfg.satp_mode); } }