| Message ID | 20221129103509.9958-4-hayashi.kunihiko@socionext.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bidnings: soc: Introduce UniPhier miscelaneous register blocks | expand |
On Tue, 29 Nov 2022 19:35:04 +0900, Kunihiko Hayashi wrote: > Add devicetree binding schema for the peripheral block implemented on > Socionext Uniphier SoCs. > > Peripheral block implemented on Socionext UniPhier SoCs is an integrated > component of the peripherals including UART, I2C/FI2C, and SCSSI. > > Peripheral block has some function logics to control the component. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.example.dtb: perictrl@59820000: 'reset' does not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.example.dtb: perictrl@59820000: 'clock' does not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221129103509.9958-4-hayashi.kunihiko@socionext.com This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command.
On 29/11/2022 11:35, Kunihiko Hayashi wrote: > Add devicetree binding schema for the peripheral block implemented on > Socionext Uniphier SoCs. > > Peripheral block implemented on Socionext UniPhier SoCs is an integrated > component of the peripherals including UART, I2C/FI2C, and SCSSI. > > Peripheral block has some function logics to control the component. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > > diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > new file mode 100644 > index 000000000000..080b6ab3ea1a > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Socionext UniPhier peripheral block controller > + > +maintainers: > + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > + > +description: |+ > + Peripheral block implemented on Socionext UniPhier SoCs is an integrated > + component of the peripherals including UART, I2C/FI2C, and SCSSI. > + Peripheral block controller is a logic to control the component. > + > +properties: > + compatible: > + items: > + - enum: > + - socionext,uniphier-ld4-perictrl > + - socionext,uniphier-pro4-perictrl > + - socionext,uniphier-pro5-perictrl > + - socionext,uniphier-pxs2-perictrl > + - socionext,uniphier-ld6b-perictrl > + - socionext,uniphier-sld8-perictrl > + - socionext,uniphier-ld11-perictrl > + - socionext,uniphier-ld20-perictrl > + - socionext,uniphier-pxs3-perictrl > + - socionext,uniphier-nx1-perictrl > + - socionext,uniphier-perictrl > + - const: simple-mfd > + - const: syscon > + > + reg: > + maxItems: 1 > + > +patternProperties: > + "^clock-controller(@[0-9a-f]+)?$": > + $ref: /schemas/clock/socionext,uniphier-clock.yaml# > + > + "^reset-controller(@[0-9a-f]+)?$": > + $ref: /schemas/reset/socionext,uniphier-reset.yaml# > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + syscon@59820000 { > + compatible = "socionext,uniphier-ld20-perictrl", > + "simple-mfd", "syscon"; > + reg = <0x59820000 0x200>; > + > + clock-controller { None of your children in examples and in DTS have unit addresses. However you explicitly mentioned them in the patternProperties. Do you expect adding unit addresses? Best regards, Krzysztof
Hi Krzysztof, On 2022/11/29 23:46, Krzysztof Kozlowski wrote: > On 29/11/2022 11:35, Kunihiko Hayashi wrote: >> Add devicetree binding schema for the peripheral block implemented on >> Socionext Uniphier SoCs. >> >> Peripheral block implemented on Socionext UniPhier SoCs is an integrated >> component of the peripherals including UART, I2C/FI2C, and SCSSI. >> >> Peripheral block has some function logics to control the component. >> >> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> >> --- >> .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++ >> 1 file changed, 67 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml >> >> diff --git >> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml >> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml >> new file mode 100644 >> index 000000000000..080b6ab3ea1a >> --- /dev/null >> +++ >> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml >> @@ -0,0 +1,67 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: >> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Socionext UniPhier peripheral block controller >> + >> +maintainers: >> + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> >> + >> +description: |+ >> + Peripheral block implemented on Socionext UniPhier SoCs is an >> integrated >> + component of the peripherals including UART, I2C/FI2C, and SCSSI. >> + Peripheral block controller is a logic to control the component. >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - socionext,uniphier-ld4-perictrl >> + - socionext,uniphier-pro4-perictrl >> + - socionext,uniphier-pro5-perictrl >> + - socionext,uniphier-pxs2-perictrl >> + - socionext,uniphier-ld6b-perictrl >> + - socionext,uniphier-sld8-perictrl >> + - socionext,uniphier-ld11-perictrl >> + - socionext,uniphier-ld20-perictrl >> + - socionext,uniphier-pxs3-perictrl >> + - socionext,uniphier-nx1-perictrl >> + - socionext,uniphier-perictrl >> + - const: simple-mfd >> + - const: syscon >> + >> + reg: >> + maxItems: 1 >> + >> +patternProperties: >> + "^clock-controller(@[0-9a-f]+)?$": >> + $ref: /schemas/clock/socionext,uniphier-clock.yaml# >> + >> + "^reset-controller(@[0-9a-f]+)?$": >> + $ref: /schemas/reset/socionext,uniphier-reset.yaml# >> + >> +required: >> + - compatible >> + - reg >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + syscon@59820000 { >> + compatible = "socionext,uniphier-ld20-perictrl", >> + "simple-mfd", "syscon"; >> + reg = <0x59820000 0x200>; >> + >> + clock-controller { > > None of your children in examples and in DTS have unit addresses. > However you explicitly mentioned them in the patternProperties. Do you > expect adding unit addresses? Currently, children's registers are partially mixed and it's hard to specify the unit address. The address pattern was added as option for the future, however, not needed for the current implementation. I'll remove them in next. Thank you, --- Best Regards Kunihiko Hayashi
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml new file mode 100644 index 000000000000..080b6ab3ea1a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier peripheral block controller + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + Peripheral block implemented on Socionext UniPhier SoCs is an integrated + component of the peripherals including UART, I2C/FI2C, and SCSSI. + Peripheral block controller is a logic to control the component. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-perictrl + - socionext,uniphier-pro4-perictrl + - socionext,uniphier-pro5-perictrl + - socionext,uniphier-pxs2-perictrl + - socionext,uniphier-ld6b-perictrl + - socionext,uniphier-sld8-perictrl + - socionext,uniphier-ld11-perictrl + - socionext,uniphier-ld20-perictrl + - socionext,uniphier-pxs3-perictrl + - socionext,uniphier-nx1-perictrl + - socionext,uniphier-perictrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + +patternProperties: + "^clock-controller(@[0-9a-f]+)?$": + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + + "^reset-controller(@[0-9a-f]+)?$": + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@59820000 { + compatible = "socionext,uniphier-ld20-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + clock-controller { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + reset-controller { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; + };
Add devicetree binding schema for the peripheral block implemented on Socionext Uniphier SoCs. Peripheral block implemented on Socionext UniPhier SoCs is an integrated component of the peripherals including UART, I2C/FI2C, and SCSSI. Peripheral block has some function logics to control the component. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml