| Message ID | 20221129143012.1806274-1-ardb@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] arm64: mm: Align PGDs to at least 64 bytes | expand |
On Tue, 29 Nov 2022 14:30:12 +0000, Ard Biesheuvel <ardb@kernel.org> wrote: > > My copy of the ARM ARM (DDI 0487I.a) no longer describes the 64 byte > minimum alignment of root page tables as being conditional on whether > 52-bit physical addressing is supported and enabled, even though I seem > to remember that this was the case formerly (and our code suggests the > same). > > Section D17.2.144 "TTBR0_EL1, Translation Table Base Register 0 (EL1)" > contains the following wording: > > ----Note---- > A translation table is required to be aligned to the size of the > table. If a table contains fewer than eight entries, it must be > aligned on a 64 byte address boundary > > So align pgd_t[] allocations to 64 bytes. Note that this change only > affects 16k/4 levels configurations, which are unlikely to be in wide > use. > > Signed-off-by: Ard Biesheuvel <ardb@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> After the VTTBR discussion, and to be extra sure of this, I reached out to ARM and asked for clarification. As it turns out, the omission of the "> 48 bits" restriction is an unfortunate specification bug, and the old behaviour still applies (Rule KBLCR is also wrong). Can't wait for the next revision! ;-) M.
On Tue, 29 Nov 2022 at 18:52, Marc Zyngier <maz@kernel.org> wrote: > > On Tue, 29 Nov 2022 14:30:12 +0000, > Ard Biesheuvel <ardb@kernel.org> wrote: > > > > My copy of the ARM ARM (DDI 0487I.a) no longer describes the 64 byte > > minimum alignment of root page tables as being conditional on whether > > 52-bit physical addressing is supported and enabled, even though I seem > > to remember that this was the case formerly (and our code suggests the > > same). > > > > Section D17.2.144 "TTBR0_EL1, Translation Table Base Register 0 (EL1)" > > contains the following wording: > > > > ----Note---- > > A translation table is required to be aligned to the size of the > > table. If a table contains fewer than eight entries, it must be > > aligned on a 64 byte address boundary > > > > So align pgd_t[] allocations to 64 bytes. Note that this change only > > affects 16k/4 levels configurations, which are unlikely to be in wide > > use. > > > > Signed-off-by: Ard Biesheuvel <ardb@kernel.org> > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > After the VTTBR discussion, and to be extra sure of this, I reached > out to ARM and asked for clarification. > > As it turns out, the omission of the "> 48 bits" restriction is an > unfortunate specification bug, and the old behaviour still applies > (Rule KBLCR is also wrong). > > Can't wait for the next revision! ;-) > Thanks for that. This is good news - it means we at least have the freedom to choose between a 47/52 and 48/52 hybrid LPA2 config for 16k pages without the need for nasty hacks (assuming we are not interested in 52-bit PA support when running with a reduced VA size deliberately instead of due to lack of h/w support) So the patch can be disregarded then.
diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c index 4a64089e5771c1e2..48989b9c9035e8b9 100644 --- a/arch/arm64/mm/pgd.c +++ b/arch/arm64/mm/pgd.c @@ -40,17 +40,10 @@ void __init pgtable_cache_init(void) if (PGD_SIZE == PAGE_SIZE) return; -#ifdef CONFIG_ARM64_PA_BITS_52 /* - * With 52-bit physical addresses, the architecture requires the - * top-level table to be aligned to at least 64 bytes. + * Naturally aligned pgds required by the architecture, with a minimum + * alignment of 64 bytes. */ - BUILD_BUG_ON(PGD_SIZE < 64); -#endif - - /* - * Naturally aligned pgds required by the architecture. - */ - pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE, - SLAB_PANIC, NULL); + pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, + max(PGD_SIZE, 64UL), SLAB_PANIC, NULL); }