| Message ID | 20221115133105.980877-11-robert.foss@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable Display for SM8350 | expand |
On 15/11/2022 14:31, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++++++++++++++++++++++++++- > 1 file changed, 193 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 434f8e8b12c1..5c98e5cf5ad0 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x820 0x402>; > + > + status = "disabled"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + status = "disabled"; It doesn't make sense to disable mdp separately, as mdss is essentially useless without it. > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + phy-names = "dsi"; I think that was dropped as of late. > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,sm8350-dispcc"; > reg = <0 0x0af00000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <0>, > - <0>, > - <0>, > - <0>, > + <&dsi0_phy 0>, <&dsi0_phy 1>, > + <0>, <0>, > <0>, > <0>; > clock-names = "bi_tcxo", > @@ -2558,6 +2746,7 @@ dispcc: clock-controller@af00000 { > #power-domain-cells = <1>; > > power-domains = <&rpmhpd SM8350_MMCX>; > + required-opps = <&rpmhpd_opp_turbo>; A turbo vote is required for it to function? Seems a bit high.. Konrad > }; > > adsp: remoteproc@17300000 {
On Tue, 15 Nov 2022 at 14:47, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 15/11/2022 14:31, Robert Foss wrote: > > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > > nodes the display subsystem is configured to support > > one DSI output. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++++++++++++++++++++++++++- > > 1 file changed, 193 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > index 434f8e8b12c1..5c98e5cf5ad0 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > @@ -3,6 +3,7 @@ > > * Copyright (c) 2020, Linaro Limited > > */ > > > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > > @@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a800000 { > > }; > > }; > > > > + mdss: mdss@ae00000 { > > + compatible = "qcom,sm8350-mdss"; > > + reg = <0 0x0ae00000 0 0x1000>; > > + reg-names = "mdss"; > > + > > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > > + interconnect-names = "mdp0-mem", "mdp1-mem"; > > + > > + power-domains = <&dispcc MDSS_GDSC>; > > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&gcc GCC_DISP_HF_AXI_CLK>, > > + <&gcc GCC_DISP_SF_AXI_CLK>, > > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > > + clock-names = "iface", "bus", "nrt_bus", "core"; > > + > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + > > + iommus = <&apps_smmu 0x820 0x402>; > > + > > + status = "disabled"; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + mdss_mdp: display-controller@ae01000 { > > + compatible = "qcom,sm8350-dpu"; > > + reg = <0 0x0ae01000 0 0x8f000>, > > + <0 0x0aeb0000 0 0x2008>; > > + reg-names = "mdp", "vbif"; > > + > > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > > + <&gcc GCC_DISP_SF_AXI_CLK>, > > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > > + clock-names = "bus", > > + "nrt_bus", > > + "iface", > > + "lut", > > + "core", > > + "vsync"; > > + > > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > > + assigned-clock-rates = <19200000>; > > + > > + operating-points-v2 = <&mdp_opp_table>; > > + power-domains = <&rpmhpd SM8350_MMCX>; > > + > > + interrupt-parent = <&mdss>; > > + interrupts = <0>; > > + > > + status = "disabled"; > It doesn't make sense to disable mdp separately, as mdss is essentially > useless without it. Ack > > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + dpu_intf1_out: endpoint { > > + remote-endpoint = <&dsi0_in>; > > + }; > > + }; > > + }; > > + > > + mdp_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-200000000 { > > + opp-hz = /bits/ 64 <200000000>; > > + required-opps = <&rpmhpd_opp_low_svs>; > > + }; > > + > > + opp-300000000 { > > + opp-hz = /bits/ 64 <300000000>; > > + required-opps = <&rpmhpd_opp_svs>; > > + }; > > + > > + opp-345000000 { > > + opp-hz = /bits/ 64 <345000000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > + > > + opp-460000000 { > > + opp-hz = /bits/ 64 <460000000>; > > + required-opps = <&rpmhpd_opp_nom>; > > + }; > > + }; > > + }; > > + > > + dsi0: dsi@ae94000 { > > + compatible = "qcom,mdss-dsi-ctrl"; > > + reg = <0 0x0ae94000 0 0x400>; > > + reg-names = "dsi_ctrl"; > > + > > + interrupt-parent = <&mdss>; > > + interrupts = <4>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&gcc GCC_DISP_HF_AXI_CLK>; > > + clock-names = "byte", > > + "byte_intf", > > + "pixel", > > + "core", > > + "iface", > > + "bus"; > > + > > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > > + assigned-clock-parents = <&dsi0_phy 0>, > > + <&dsi0_phy 1>; > > + > > + operating-points-v2 = <&dsi_opp_table>; > > + power-domains = <&rpmhpd SM8350_MMCX>; > > + > > + phys = <&dsi0_phy>; > > + phy-names = "dsi"; > I think that was dropped as of late. Ack > > > + > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + dsi0_in: endpoint { > > + remote-endpoint = <&dpu_intf1_out>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + dsi0_out: endpoint { > > + }; > > + }; > > + }; > > + }; > > + > > + dsi0_phy: phy@ae94400 { > > + compatible = "qcom,dsi-phy-5nm-8350"; > > + reg = <0 0x0ae94400 0 0x200>, > > + <0 0x0ae94600 0 0x280>, > > + <0 0x0ae94900 0 0x260>; > > + reg-names = "dsi_phy", > > + "dsi_phy_lane", > > + "dsi_pll"; > > + > > + #clock-cells = <1>; > > + #phy-cells = <0>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "iface", "ref"; > > + > > + status = "disabled"; > > + > > + dsi_opp_table: dsi-opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-187500000 { > > + opp-hz = /bits/ 64 <187500000>; > > + required-opps = <&rpmhpd_opp_low_svs>; > > + }; > > + > > + opp-300000000 { > > + opp-hz = /bits/ 64 <300000000>; > > + required-opps = <&rpmhpd_opp_svs>; > > + }; > > + > > + opp-358000000 { > > + opp-hz = /bits/ 64 <358000000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > + }; > > + }; > > + }; > > + > > dispcc: clock-controller@af00000 { > > compatible = "qcom,sm8350-dispcc"; > > reg = <0 0x0af00000 0 0x10000>; > > clocks = <&rpmhcc RPMH_CXO_CLK>, > > - <0>, > > - <0>, > > - <0>, > > - <0>, > > + <&dsi0_phy 0>, <&dsi0_phy 1>, > > + <0>, <0>, > > <0>, > > <0>; > > clock-names = "bi_tcxo", > > @@ -2558,6 +2746,7 @@ dispcc: clock-controller@af00000 { > > #power-domain-cells = <1>; > > > > power-domains = <&rpmhpd SM8350_MMCX>; > > + required-opps = <&rpmhpd_opp_turbo>; > A turbo vote is required for it to function? Seems a bit high.. Dmitry hit a snag using &rpmhpd_opp_low_svs, so this was a dummy value. I can't replicate that issue, but am having a conversation with him off-list about this. On my sm8350-hdk board &rpmhpd_opp_low_svs is working fine. > > Konrad > > }; > > > > adsp: remoteproc@17300000 {
On 29/11/2022 18:47, Robert Foss wrote: > On Tue, 15 Nov 2022 at 14:47, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >> >> >> >> On 15/11/2022 14:31, Robert Foss wrote: >>> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these >>> nodes the display subsystem is configured to support >>> one DSI output. >>> >>> Signed-off-by: Robert Foss <robert.foss@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++++++++++++++++++++++++++- >>> 1 file changed, 193 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> index 434f8e8b12c1..5c98e5cf5ad0 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi >>> @@ -3,6 +3,7 @@ >>> * Copyright (c) 2020, Linaro Limited >>> */ >>> >>> +#include <dt-bindings/interconnect/qcom,sm8350.h> >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> #include <dt-bindings/clock/qcom,dispcc-sm8350.h> >>> #include <dt-bindings/clock/qcom,gcc-sm8350.h> >>> @@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a800000 { >>> }; >>> }; >>> >>> + mdss: mdss@ae00000 { >>> + compatible = "qcom,sm8350-mdss"; >>> + reg = <0 0x0ae00000 0 0x1000>; >>> + reg-names = "mdss"; >>> + >>> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, >>> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; >>> + interconnect-names = "mdp0-mem", "mdp1-mem"; >>> + >>> + power-domains = <&dispcc MDSS_GDSC>; >>> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; >>> + >>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&gcc GCC_DISP_HF_AXI_CLK>, >>> + <&gcc GCC_DISP_SF_AXI_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_CLK>; >>> + clock-names = "iface", "bus", "nrt_bus", "core"; >>> + >>> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; >>> + interrupt-controller; >>> + #interrupt-cells = <1>; >>> + >>> + iommus = <&apps_smmu 0x820 0x402>; >>> + >>> + status = "disabled"; >>> + >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + >>> + mdss_mdp: display-controller@ae01000 { >>> + compatible = "qcom,sm8350-dpu"; >>> + reg = <0 0x0ae01000 0 0x8f000>, >>> + <0 0x0aeb0000 0 0x2008>; >>> + reg-names = "mdp", "vbif"; >>> + >>> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >>> + <&gcc GCC_DISP_SF_AXI_CLK>, >>> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >>> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>> + clock-names = "bus", >>> + "nrt_bus", >>> + "iface", >>> + "lut", >>> + "core", >>> + "vsync"; >>> + >>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >>> + assigned-clock-rates = <19200000>; >>> + >>> + operating-points-v2 = <&mdp_opp_table>; >>> + power-domains = <&rpmhpd SM8350_MMCX>; >>> + >>> + interrupt-parent = <&mdss>; >>> + interrupts = <0>; >>> + >>> + status = "disabled"; >> It doesn't make sense to disable mdp separately, as mdss is essentially >> useless without it. > > Ack > >> >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + dpu_intf1_out: endpoint { >>> + remote-endpoint = <&dsi0_in>; >>> + }; >>> + }; >>> + }; >>> + >>> + mdp_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-200000000 { >>> + opp-hz = /bits/ 64 <200000000>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-300000000 { >>> + opp-hz = /bits/ 64 <300000000>; >>> + required-opps = <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-345000000 { >>> + opp-hz = /bits/ 64 <345000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >>> + >>> + opp-460000000 { >>> + opp-hz = /bits/ 64 <460000000>; >>> + required-opps = <&rpmhpd_opp_nom>; >>> + }; >>> + }; >>> + }; >>> + >>> + dsi0: dsi@ae94000 { >>> + compatible = "qcom,mdss-dsi-ctrl"; >>> + reg = <0 0x0ae94000 0 0x400>; >>> + reg-names = "dsi_ctrl"; >>> + >>> + interrupt-parent = <&mdss>; >>> + interrupts = <4>; >>> + >>> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, >>> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, >>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, >>> + <&dispcc DISP_CC_MDSS_ESC0_CLK>, >>> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&gcc GCC_DISP_HF_AXI_CLK>; >>> + clock-names = "byte", >>> + "byte_intf", >>> + "pixel", >>> + "core", >>> + "iface", >>> + "bus"; >>> + >>> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, >>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; >>> + assigned-clock-parents = <&dsi0_phy 0>, >>> + <&dsi0_phy 1>; >>> + >>> + operating-points-v2 = <&dsi_opp_table>; >>> + power-domains = <&rpmhpd SM8350_MMCX>; >>> + >>> + phys = <&dsi0_phy>; >>> + phy-names = "dsi"; >> I think that was dropped as of late. > > Ack > >> >>> + >>> + status = "disabled"; >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + dsi0_in: endpoint { >>> + remote-endpoint = <&dpu_intf1_out>; >>> + }; >>> + }; >>> + >>> + port@1 { >>> + reg = <1>; >>> + dsi0_out: endpoint { >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> + dsi0_phy: phy@ae94400 { >>> + compatible = "qcom,dsi-phy-5nm-8350"; >>> + reg = <0 0x0ae94400 0 0x200>, >>> + <0 0x0ae94600 0 0x280>, >>> + <0 0x0ae94900 0 0x260>; >>> + reg-names = "dsi_phy", >>> + "dsi_phy_lane", >>> + "dsi_pll"; >>> + >>> + #clock-cells = <1>; >>> + #phy-cells = <0>; >>> + >>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >>> + <&rpmhcc RPMH_CXO_CLK>; >>> + clock-names = "iface", "ref"; >>> + >>> + status = "disabled"; >>> + >>> + dsi_opp_table: dsi-opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-187500000 { >>> + opp-hz = /bits/ 64 <187500000>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + }; >>> + >>> + opp-300000000 { >>> + opp-hz = /bits/ 64 <300000000>; >>> + required-opps = <&rpmhpd_opp_svs>; >>> + }; >>> + >>> + opp-358000000 { >>> + opp-hz = /bits/ 64 <358000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> dispcc: clock-controller@af00000 { >>> compatible = "qcom,sm8350-dispcc"; >>> reg = <0 0x0af00000 0 0x10000>; >>> clocks = <&rpmhcc RPMH_CXO_CLK>, >>> - <0>, >>> - <0>, >>> - <0>, >>> - <0>, >>> + <&dsi0_phy 0>, <&dsi0_phy 1>, >>> + <0>, <0>, >>> <0>, >>> <0>; >>> clock-names = "bi_tcxo", >>> @@ -2558,6 +2746,7 @@ dispcc: clock-controller@af00000 { >>> #power-domain-cells = <1>; >>> >>> power-domains = <&rpmhpd SM8350_MMCX>; >>> + required-opps = <&rpmhpd_opp_turbo>; >> A turbo vote is required for it to function? Seems a bit high.. > > Dmitry hit a snag using &rpmhpd_opp_low_svs, so this was a dummy > value. I can't replicate that issue, but am having a conversation with > him off-list about this. > > On my sm8350-hdk board &rpmhpd_opp_low_svs is working fine. Maybe this is related to the bootloader setting up the mode or maybe it was caused by the fact that I have the drm_msm set up as built-in rather than a module. > >> >> Konrad >>> }; >>> >>> adsp: remoteproc@17300000 {
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 434f8e8b12c1..5c98e5cf5ad0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> @@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8350"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8350-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", @@ -2558,6 +2746,7 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_turbo>; }; adsp: remoteproc@17300000 {
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++++++++++++++++++++++++++- 1 file changed, 193 insertions(+), 4 deletions(-)