| Message ID | 20221115200832.706370-1-jamie@jamieiles.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V: Dynamic ftrace support for RV32I | expand |
On Tue, Nov 15, 2022 at 08:08:28PM +0000, Jamie Iles wrote: > This series enables dynamic ftrace support for RV32I bringing it to > parity with RV64I. Most of the work is already there, this is largely > just assembly fixes to handle register sizes, correct handling of the > psABI calling convention and Kconfig change. > > Validated with all ftrace boot time self test with qemu for RV32I and > RV64I in addition to real tracing on an RV32I FPGA design. > > Changes since v1 > (http://lists.infradead.org/pipermail/linux-riscv/2022-October/021103.html) > > - Fixed the use of SZREG in patch 2 > > Jamie Iles (4): > RISC-V: use REG_S/REG_L for mcount > RISC-V: reduce mcount save space on RV32 > RISC-V: preserve a1 in mcount > RISC-V: enable dynamic ftrace for RV32I > > arch/riscv/Kconfig | 10 ++++----- > arch/riscv/kernel/mcount.S | 44 ++++++++++++++++++++------------------ > 2 files changed, 28 insertions(+), 26 deletions(-) Hi Jamie, Please CC previous reviewers on the entire series when reposting. Thanks, drew > > -- > 2.37.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, 15 Nov 2022 20:08:28 +0000, Jamie Iles wrote: > This series enables dynamic ftrace support for RV32I bringing it to > parity with RV64I. Most of the work is already there, this is largely > just assembly fixes to handle register sizes, correct handling of the > psABI calling convention and Kconfig change. > > Validated with all ftrace boot time self test with qemu for RV32I and > RV64I in addition to real tracing on an RV32I FPGA design. > > [...] Applied, thanks! [1/4] RISC-V: use REG_S/REG_L for mcount https://git.kernel.org/palmer/c/8a6841c439df [2/4] RISC-V: reduce mcount save space on RV32 https://git.kernel.org/palmer/c/3bd7743f8d6d [3/4] RISC-V: preserve a1 in mcount https://git.kernel.org/palmer/c/dc58a24db8c1 [4/4] RISC-V: enable dynamic ftrace for RV32I https://git.kernel.org/palmer/c/f32b4b467ebd Best regards,
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Tue, 15 Nov 2022 20:08:28 +0000 you wrote: > This series enables dynamic ftrace support for RV32I bringing it to > parity with RV64I. Most of the work is already there, this is largely > just assembly fixes to handle register sizes, correct handling of the > psABI calling convention and Kconfig change. > > Validated with all ftrace boot time self test with qemu for RV32I and > RV64I in addition to real tracing on an RV32I FPGA design. > > [...] Here is the summary with links: - [v2,1/4] RISC-V: use REG_S/REG_L for mcount https://git.kernel.org/riscv/c/8a6841c439df - [v2,2/4] RISC-V: reduce mcount save space on RV32 https://git.kernel.org/riscv/c/3bd7743f8d6d - [v2,3/4] RISC-V: preserve a1 in mcount https://git.kernel.org/riscv/c/dc58a24db8c1 - [v2,4/4] RISC-V: enable dynamic ftrace for RV32I https://git.kernel.org/riscv/c/f32b4b467ebd You are awesome, thank you!