| Message ID | 20221205174433.16847-14-quic_bjorande@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: Add SC8280XP support | expand |
On 05/12/2022 18:44, Bjorn Andersson wrote: > From: Bjorn Andersson <bjorn.andersson@linaro.org> > > The SA8295P ADP has, among other interfaces, six MiniDP connectors which > are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. > > Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, > DP PHYs and link them all together. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > > Changes since v3: > - None > > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++++++++++++++++++++++- > 1 file changed, 241 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > index 6c29d7d757e0..d55c8c5304cc 100644 > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > @@ -23,6 +23,90 @@ aliases { > chosen { > stdout-path = "serial0:115200n8"; > }; > + > + dp2-connector { > + compatible = "dp-connector"; > + label = "DP2"; > + type = "mini"; > + > + hpd-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; > + > + port { > + dp2_connector_in: endpoint { > + remote-endpoint = <&mdss1_dp0_phy_out>; > + }; > + }; > + }; > + > + dp3-connector { > + compatible = "dp-connector"; > + label = "DP3"; > + type = "mini"; > + > + hpd-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; > + > + port { > + dp3_connector_in: endpoint { > + remote-endpoint = <&mdss1_dp1_phy_out>; > + }; > + }; > + }; > + > + edp0-connector { > + compatible = "dp-connector"; > + label = "EDP0"; > + type = "mini"; > + > + hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; > + > + port { > + edp0_connector_in: endpoint { > + remote-endpoint = <&mdss0_dp2_phy_out>; > + }; > + }; > + }; > + > + edp1-connector { > + compatible = "dp-connector"; > + label = "EDP1"; > + type = "mini"; > + > + hpd-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; > + > + port { > + edp1_connector_in: endpoint { > + remote-endpoint = <&mdss0_dp3_phy_out>; > + }; > + }; > + }; > + > + edp2-connector { > + compatible = "dp-connector"; > + label = "EDP2"; > + type = "mini"; > + > + hpd-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; > + > + port { > + edp2_connector_in: endpoint { > + remote-endpoint = <&mdss1_dp2_phy_out>; > + }; > + }; > + }; > + > + edp3-connector { > + compatible = "dp-connector"; > + label = "EDP3"; > + type = "mini"; > + > + hpd-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; > + > + port { > + edp3_connector_in: endpoint { > + remote-endpoint = <&mdss1_dp3_phy_out>; > + }; > + }; > + }; > }; > > &apps_rsc { > @@ -163,13 +247,168 @@ vreg_l7g: ldo7 { > > vreg_l8g: ldo8 { > regulator-name = "vreg_l8g"; > - regulator-min-microvolt = <880000>; > - regulator-max-microvolt = <880000>; > + regulator-min-microvolt = <912000>; > + regulator-max-microvolt = <912000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > + }; > + > + vreg_l11g: ldo11 { > + regulator-name = "vreg_l11g"; > + regulator-min-microvolt = <912000>; > + regulator-max-microvolt = <912000>; > regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; > }; > }; > }; > > +&dispcc0 { > + status = "okay"; > +}; > + > +&dispcc1 { > + status = "okay"; > +}; > + > +&mdss0 { > + status = "okay"; > +}; > + > +&mdss0_dp2 { > + status = "okay"; status should go last. > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss0_dp2_phy_out: endpoint { That's quite a lot of indentation.. couldn't these endpoints be defined in the SoC DT? Konrad > + remote-endpoint = <&edp0_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss0_dp2_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l8g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss0_dp3 { > + status = "okay"; > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss0_dp3_phy_out: endpoint { > + remote-endpoint = <&edp1_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss0_dp3_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l8g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1 { > + status = "okay"; > +}; > + > +&mdss1_dp0 { > + status = "okay"; > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp0_phy_out: endpoint { > + remote-endpoint = <&dp2_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp0_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1_dp1 { > + status = "okay"; > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp1_phy_out: endpoint { > + remote-endpoint = <&dp3_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp1_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1_dp2 { > + status = "okay"; > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp2_phy_out: endpoint { > + remote-endpoint = <&edp2_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp2_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > +&mdss1_dp3 { > + status = "okay"; > + > + data-lanes = <0 1 2 3>; > + > + ports { > + port@1 { > + reg = <1>; > + mdss1_dp3_phy_out: endpoint { > + remote-endpoint = <&edp3_connector_in>; > + }; > + }; > + }; > +}; > + > +&mdss1_dp3_phy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l11g>; > + vdda-pll-supply = <&vreg_l3g>; > +}; > + > &pcie2a { > perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
On Mon, Dec 05, 2022 at 07:09:45PM +0100, Konrad Dybcio wrote: > On 05/12/2022 18:44, Bjorn Andersson wrote: > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts [..] > > +&mdss0_dp2 { > > + status = "okay"; > status should go last. > Thanks for pointing that out. Would be nice if the computer told me that...somehow... > > + > > + data-lanes = <0 1 2 3>; > > + > > + ports { > > + port@1 { > > + reg = <1>; > > + mdss0_dp2_phy_out: endpoint { > That's quite a lot of indentation.. couldn't these endpoints be defined in > the SoC DT? > The alternative would be to have the description of each DP controller split over multiple nodes and rely on the reader to stitch together the view of the node based on the label. Based on the naming of these labels they would at least be adjacent, so it wouldn't be that bad. But I feel that there is enough DP-controller nodes in this board already; I've yet to describe the two USB Type-C controllers or the two DSI-DP bridges. So I don't know if it's worth optimizing indentation-level within each node like this. And we will end up mixing this optimization between DP controllers, USB Type-C nodes, QMP nodes, DSI-DP bridges. Regards, Bjorn
On 05/12/2022 21:02, Bjorn Andersson wrote: > On Mon, Dec 05, 2022 at 07:09:45PM +0100, Konrad Dybcio wrote: >> On 05/12/2022 18:44, Bjorn Andersson wrote: >>> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > [..] >>> +&mdss0_dp2 { >>> + status = "okay"; >> status should go last. >> > > Thanks for pointing that out. Would be nice if the computer told me > that...somehow... > >>> + >>> + data-lanes = <0 1 2 3>; >>> + >>> + ports { >>> + port@1 { >>> + reg = <1>; >>> + mdss0_dp2_phy_out: endpoint { >> That's quite a lot of indentation.. couldn't these endpoints be defined in >> the SoC DT? >> > > The alternative would be to have the description of each DP controller > split over multiple nodes and rely on the reader to stitch together the > view of the node based on the label. > Based on the naming of these labels they would at least be adjacent, so > it wouldn't be that bad. > > But I feel that there is enough DP-controller nodes in this board > already; I've yet to describe the two USB Type-C controllers or the two > DSI-DP bridges. > So I don't know if it's worth optimizing indentation-level within each > node like this. > > > And we will end up mixing this optimization between DP controllers, USB > Type-C nodes, QMP nodes, DSI-DP bridges. Oh okay, I see, let's keep it as-is then. Konrad > > Regards, > Bjorn
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 6c29d7d757e0..d55c8c5304cc 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -23,6 +23,90 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + dp2-connector { + compatible = "dp-connector"; + label = "DP2"; + type = "mini"; + + hpd-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_phy_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "DP3"; + type = "mini"; + + hpd-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_phy_out>; + }; + }; + }; + + edp0-connector { + compatible = "dp-connector"; + label = "EDP0"; + type = "mini"; + + hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + + port { + edp0_connector_in: endpoint { + remote-endpoint = <&mdss0_dp2_phy_out>; + }; + }; + }; + + edp1-connector { + compatible = "dp-connector"; + label = "EDP1"; + type = "mini"; + + hpd-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + port { + edp1_connector_in: endpoint { + remote-endpoint = <&mdss0_dp3_phy_out>; + }; + }; + }; + + edp2-connector { + compatible = "dp-connector"; + label = "EDP2"; + type = "mini"; + + hpd-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + port { + edp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp2_phy_out>; + }; + }; + }; + + edp3-connector { + compatible = "dp-connector"; + label = "EDP3"; + type = "mini"; + + hpd-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + port { + edp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp3_phy_out>; + }; + }; + }; }; &apps_rsc { @@ -163,13 +247,168 @@ vreg_l7g: ldo7 { vreg_l8g: ldo8 { regulator-name = "vreg_l8g"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11g: ldo11 { + regulator-name = "vreg_l11g"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; }; }; +&dispcc0 { + status = "okay"; +}; + +&dispcc1 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp2 { + status = "okay"; + + data-lanes = <0 1 2 3>; + + ports { + port@1 { + reg = <1>; + mdss0_dp2_phy_out: endpoint { + remote-endpoint = <&edp0_connector_in>; + }; + }; + }; +}; + +&mdss0_dp2_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; +}; + +&mdss0_dp3 { + status = "okay"; + + data-lanes = <0 1 2 3>; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_phy_out: endpoint { + remote-endpoint = <&edp1_connector_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; +}; + +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + status = "okay"; + + data-lanes = <0 1 2 3>; + + ports { + port@1 { + reg = <1>; + mdss1_dp0_phy_out: endpoint { + remote-endpoint = <&dp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; +}; + +&mdss1_dp1 { + status = "okay"; + + data-lanes = <0 1 2 3>; + + ports { + port@1 { + reg = <1>; + mdss1_dp1_phy_out: endpoint { + remote-endpoint = <&dp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp1_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; +}; + +&mdss1_dp2 { + status = "okay"; + + data-lanes = <0 1 2 3>; + + ports { + port@1 { + reg = <1>; + mdss1_dp2_phy_out: endpoint { + remote-endpoint = <&edp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp2_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; +}; + +&mdss1_dp3 { + status = "okay"; + + data-lanes = <0 1 2 3>; + + ports { + port@1 { + reg = <1>; + mdss1_dp3_phy_out: endpoint { + remote-endpoint = <&edp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp3_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;