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[1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

Message ID 20221205050038.195746-1-bmeng@tinylab.org (mailing list archive)
State Superseded
Delegated to: Palmer Dabbelt
Headers show
Series [1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V | expand

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Commit Message

Bin Meng Dec. 5, 2022, 5 a.m. UTC
Per RISC-V semihosting spec [1], adapt the existing Arm semihosting
earlycon driver to RISC-V.

[1] https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Bin Meng <bmeng@tinylab.org>
---

 drivers/tty/serial/Kconfig                 |  2 +-
 drivers/tty/serial/earlycon-arm-semihost.c | 17 ++++++++++++++++-
 2 files changed, 17 insertions(+), 2 deletions(-)

Comments

Jiri Slaby Dec. 6, 2022, 6:35 a.m. UTC | #1
On 05. 12. 22, 6:00, Bin Meng wrote:
...
> --- a/drivers/tty/serial/earlycon-arm-semihost.c
> +++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
> @@ -23,7 +27,18 @@
>    */
>   static void smh_putc(struct uart_port *port, unsigned char c)
>   {
> -#ifdef CONFIG_ARM64
> +#if defined(CONFIG_RISCV)
> +	asm volatile("addi    a1, %0, 0\n"
> +		     "addi    a0, zero, 3\n"
> +		     ".balign 16\n"
> +		     ".option push\n"
> +		     ".option norvc\n"
> +		     "slli    zero, zero, 0x1f\n"
> +		     "ebreak\n"
> +		     "srai    zero, zero, 0x7\n"
> +		     ".option pop\n"
> +		     : : "r" (&c) : "a0", "a1", "memory");
> +#elif defined(CONFIG_ARM64)
>   	asm volatile("mov  x1, %0\n"
>   		     "mov  x0, #3\n"
>   		     "hlt  0xf000\n"

Hmm, can we implement all those smh_putc() variants in respective 
arch/*/include/semihost.h instead?

thanks,
Bin Meng Dec. 6, 2022, 2:23 p.m. UTC | #2
On Tue, Dec 6, 2022 at 2:47 PM Jiri Slaby <jirislaby@kernel.org> wrote:
>
> On 05. 12. 22, 6:00, Bin Meng wrote:
> ...
> > --- a/drivers/tty/serial/earlycon-arm-semihost.c
> > +++ b/drivers/tty/serial/earlycon-arm-semihost.c
> ...
> > @@ -23,7 +27,18 @@
> >    */
> >   static void smh_putc(struct uart_port *port, unsigned char c)
> >   {
> > -#ifdef CONFIG_ARM64
> > +#if defined(CONFIG_RISCV)
> > +     asm volatile("addi    a1, %0, 0\n"
> > +                  "addi    a0, zero, 3\n"
> > +                  ".balign 16\n"
> > +                  ".option push\n"
> > +                  ".option norvc\n"
> > +                  "slli    zero, zero, 0x1f\n"
> > +                  "ebreak\n"
> > +                  "srai    zero, zero, 0x7\n"
> > +                  ".option pop\n"
> > +                  : : "r" (&c) : "a0", "a1", "memory");
> > +#elif defined(CONFIG_ARM64)
> >       asm volatile("mov  x1, %0\n"
> >                    "mov  x0, #3\n"
> >                    "hlt  0xf000\n"
>
> Hmm, can we implement all those smh_putc() variants in respective
> arch/*/include/semihost.h instead?
>

I think so. Will do in v2.

Regards,
Bin
diff mbox series

Patch

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 434f83168546..e94d1265151c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -75,7 +75,7 @@  config SERIAL_AMBA_PL011_CONSOLE
 
 config SERIAL_EARLYCON_ARM_SEMIHOST
 	bool "Early console using ARM semihosting"
-	depends on ARM64 || ARM
+	depends on ARM64 || ARM || RISCV
 	select SERIAL_CORE
 	select SERIAL_CORE_CONSOLE
 	select SERIAL_EARLYCON
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
index fcdec5f42376..25a0f91926a3 100644
--- a/drivers/tty/serial/earlycon-arm-semihost.c
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
@@ -6,6 +6,10 @@ 
  * Adapted for ARM and earlycon:
  * Copyright (C) 2014 Linaro Ltd.
  * Author: Rob Herring <robh@kernel.org>
+ *
+ * Adapted for RISC-V and earlycon:
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
  */
 #include <linux/kernel.h>
 #include <linux/console.h>
@@ -23,7 +27,18 @@ 
  */
 static void smh_putc(struct uart_port *port, unsigned char c)
 {
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_RISCV)
+	asm volatile("addi    a1, %0, 0\n"
+		     "addi    a0, zero, 3\n"
+		     ".balign 16\n"
+		     ".option push\n"
+		     ".option norvc\n"
+		     "slli    zero, zero, 0x1f\n"
+		     "ebreak\n"
+		     "srai    zero, zero, 0x7\n"
+		     ".option pop\n"
+		     : : "r" (&c) : "a0", "a1", "memory");
+#elif defined(CONFIG_ARM64)
 	asm volatile("mov  x1, %0\n"
 		     "mov  x0, #3\n"
 		     "hlt  0xf000\n"