| Message ID | 20221213160112.1900410-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells | expand |
Thanks! This patch series makes PCIe work for me on "Nitrogen8M PLUS SOM" by
Boundary Devices, used with adapter on MNT Reform 2 motherboard, routed
to mPCIe card (in this case an ath9k card).
Tested-by: Lukas F. Hartmann <lukas@mntre.com>
Best
Lukas
On Tue, 13 Dec 2022 17:01:09 +0100, Lucas Stach wrote: > The HSIO blk-ctrl has a internal PLL, which can be used as a reference > clock for the PCIe PHY. Add clock-cells to the binding to allow the > driver to expose this PLL. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.example.dtb: blk-ctrl@32f10000: #clock-cells:0:0: 1 was expected From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221213160112.1900410-1-l.stach@pengutronix.de The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Sali Lucas On Tue, 2022-12-13 at 17:01 +0100, Lucas Stach wrote: > The HSIO blk-ctrl has a internal PLL, which can be used as a reference > clock for the PCIe PHY. Add clock-cells to the binding to allow the > driver to expose this PLL. Nice! This indeed works fine on Verdin iMX8M Plus as well. Thanks! > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Entire series: Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > --- > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > index c29181a9745b..1cc7c2bdf2bb 100644 > --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > @@ -39,6 +39,9 @@ properties: > - const: pcie > - const: pcie-phy > > + '#clock-cells': > + const: 1 > + > clocks: > minItems: 2 > maxItems: 2 > @@ -85,4 +88,5 @@ examples: > power-domain-names = "bus", "usb", "usb-phy1", > "usb-phy2", "pcie", "pcie-phy"; > #power-domain-cells = <1>; > + #clock-cells = <0>; > };
Hi Lucas:
Thanks a lot for your help about this series.
Should the clocks of the pcie_phy should be changed as below when internal
PLL is used as PCIe reference clock on i.MX8MP EVK board?
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -370,7 +370,7 @@ &i2c5 {
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- clocks = <&pcie0_refclk>;
+ clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
status = "okay";
};
Best Regards
Richard Zhu
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年12月14日 0:01
> To: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Shawn Guo <shawnguo@kernel.org>;
> Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: dl-linux-imx <linux-imx@nxp.com>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
> marex@denx.de; tharvey@gateworks.com; alexander.stein@ew.tq-group.com;
> richard.leitner@linux.dev; lukas@mntre.com; patchwork-lst@pengutronix.de;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: [PATCH 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells
>
> The HSIO blk-ctrl has a internal PLL, which can be used as a reference clock for
> the PCIe PHY. Add clock-cells to the binding to allow the driver to expose this
> PLL.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> index c29181a9745b..1cc7c2bdf2bb 100644
> ---
> a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl
> +++ .yaml
> @@ -39,6 +39,9 @@ properties:
> - const: pcie
> - const: pcie-phy
>
> + '#clock-cells':
> + const: 1
> +
> clocks:
> minItems: 2
> maxItems: 2
> @@ -85,4 +88,5 @@ examples:
> power-domain-names = "bus", "usb", "usb-phy1",
> "usb-phy2", "pcie", "pcie-phy";
> #power-domain-cells = <1>;
> + #clock-cells = <0>;
> };
> --
> 2.30.2
On Wed, 2022-12-14 at 05:51 +0000, Hongxing Zhu wrote: > Hi Lucas: > Thanks a lot for your help about this series. > > Should the clocks of the pcie_phy should be changed as below when internal > PLL is used as PCIe reference clock on i.MX8MP EVK board? > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > @@ -370,7 +370,7 @@ &i2c5 { > > &pcie_phy { > fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; > - clocks = <&pcie0_refclk>; > + clocks = <&hsio_blk_ctrl>; Yes, exactly. See e.g. also [1]. But don't forget to also change the fsl,refclk-pad-mode to IMX8_PCIE_REFCLK_PAD_OUTPUT (;-p). [1] https://lore.kernel.org/all/20221214061354.174072-1-marcel@ziswiler.com/ > clock-names = "ref"; > status = "okay"; > }; > > Best Regards > Richard Zhu > > > -----Original Message----- > > From: Lucas Stach <l.stach@pengutronix.de> > > Sent: 2022年12月14日 0:01 > > To: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski > > <krzysztof.kozlowski+dt@linaro.org>; Shawn Guo <shawnguo@kernel.org>; > > Hongxing Zhu <hongxing.zhu@nxp.com> > > Cc: dl-linux-imx <linux-imx@nxp.com>; Pengutronix Kernel Team > > <kernel@pengutronix.de>; Marcel Ziswiler <marcel.ziswiler@toradex.com>; > > marex@denx.de; tharvey@gateworks.com; alexander.stein@ew.tq-group.com; > > richard.leitner@linux.dev; lukas@mntre.com; patchwork-lst@pengutronix.de; > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org > > Subject: [PATCH 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells > > > > The HSIO blk-ctrl has a internal PLL, which can be used as a reference clock for > > the PCIe PHY. Add clock-cells to the binding to allow the driver to expose this > > PLL. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > > index c29181a9745b..1cc7c2bdf2bb 100644 > > --- > > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl > > +++ .yaml > > @@ -39,6 +39,9 @@ properties: > > - const: pcie > > - const: pcie-phy > > > > + '#clock-cells': > > + const: 1 > > + > > clocks: > > minItems: 2 > > maxItems: 2 > > @@ -85,4 +88,5 @@ examples: > > power-domain-names = "bus", "usb", "usb-phy1", > > "usb-phy2", "pcie", "pcie-phy"; > > #power-domain-cells = <1>; > > + #clock-cells = <0>; > > }; > > -- > > 2.30.2
Hi Lucas, Am Dienstag, 13. Dezember 2022, 17:01:09 CET schrieb Lucas Stach: > The HSIO blk-ctrl has a internal PLL, which can be used as a reference > clock for the PCIe PHY. Add clock-cells to the binding to allow the > driver to expose this PLL. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > index c29181a9745b..1cc7c2bdf2bb 100644 > --- > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > +++ > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > @@ -39,6 +39,9 @@ properties: > - const: pcie > - const: pcie-phy > > + '#clock-cells': > + const: 1 Rob's bot already noticed the mismatch between this and the example. Best regards, Alexander > + > clocks: > minItems: 2 > maxItems: 2 > @@ -85,4 +88,5 @@ examples: > power-domain-names = "bus", "usb", "usb-phy1", > "usb-phy2", "pcie", "pcie-phy"; > #power-domain-cells = <1>; > + #clock-cells = <0>; > };
> -----Original Message----- > From: Marcel Ziswiler <marcel.ziswiler@toradex.com> > Sent: 2022年12月14日 14:22 > To: l.stach@pengutronix.de; krzysztof.kozlowski+dt@linaro.org; Hongxing Zhu > <hongxing.zhu@nxp.com>; robh+dt@kernel.org; shawnguo@kernel.org > Cc: dl-linux-imx <linux-imx@nxp.com>; kernel@pengutronix.de; > richard.leitner@linux.dev; alexander.stein@ew.tq-group.com; > patchwork-lst@pengutronix.de; tharvey@gateworks.com; marex@denx.de; > lukas@mntre.com; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells > > On Wed, 2022-12-14 at 05:51 +0000, Hongxing Zhu wrote: > > Hi Lucas: > > Thanks a lot for your help about this series. > > > > Should the clocks of the pcie_phy should be changed as below when > > internal > > PLL is used as PCIe reference clock on i.MX8MP EVK board? > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts > > @@ -370,7 +370,7 @@ &i2c5 { > > > > &pcie_phy { > > fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; > > - clocks = <&pcie0_refclk>; > > + clocks = <&hsio_blk_ctrl>; > > Yes, exactly. See e.g. also [1]. But don't forget to also change the > fsl,refclk-pad-mode to IMX8_PCIE_REFCLK_PAD_OUTPUT (;-p). > Got that. Thanks for your reminder. Best Regards Richard Zhu > [1] > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ker > nel.org%2Fall%2F20221214061354.174072-1-marcel%40ziswiler.com%2F&am > p;data=05%7C01%7Chongxing.zhu%40nxp.com%7Cacc7c14718fe45028c2808 > dadd9b8ae7%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63806 > 5957361141610%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLC > JQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&am > p;sdata=jK7t%2Bk6EZRS8oqHzRzsHR%2FImM2RGYRp7dIwc9pX2fqE%3D& > reserved=0 > > > clock-names = "ref"; > > status = "okay"; > > }; > > > > Best Regards > > Richard Zhu > > > > > -----Original Message----- > > > From: Lucas Stach <l.stach@pengutronix.de> > > > Sent: 2022年12月14日 0:01 > > > To: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski > > > <krzysztof.kozlowski+dt@linaro.org>; Shawn Guo > > > <shawnguo@kernel.org>; Hongxing Zhu <hongxing.zhu@nxp.com> > > > Cc: dl-linux-imx <linux-imx@nxp.com>; Pengutronix Kernel Team > > > <kernel@pengutronix.de>; Marcel Ziswiler > > > <marcel.ziswiler@toradex.com>; marex@denx.de; > tharvey@gateworks.com; > > > alexander.stein@ew.tq-group.com; richard.leitner@linux.dev; > > > lukas@mntre.com; patchwork-lst@pengutronix.de; > > > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org > > > Subject: [PATCH 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add > > > clock cells > > > > > > The HSIO blk-ctrl has a internal PLL, which can be used as a > > > reference clock for the PCIe PHY. Add clock-cells to the binding to > > > allow the driver to expose this PLL. > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > --- > > > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 > > > ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl > > > .yaml > > > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl > > > .yaml index c29181a9745b..1cc7c2bdf2bb 100644 > > > --- > > > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl > > > .yaml > > > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk- > > > +++ ctrl > > > +++ .yaml > > > @@ -39,6 +39,9 @@ properties: > > > - const: pcie > > > - const: pcie-phy > > > > > > + '#clock-cells': > > > + const: 1 > > > + > > > clocks: > > > minItems: 2 > > > maxItems: 2 > > > @@ -85,4 +88,5 @@ examples: > > > power-domain-names = "bus", "usb", "usb-phy1", > > > "usb-phy2", "pcie", > "pcie-phy"; > > > #power-domain-cells = <1>; > > > + #clock-cells = <0>; > > > }; > > > -- > > > 2.30.2
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index c29181a9745b..1cc7c2bdf2bb 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -39,6 +39,9 @@ properties: - const: pcie - const: pcie-phy + '#clock-cells': + const: 1 + clocks: minItems: 2 maxItems: 2 @@ -85,4 +88,5 @@ examples: power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; #power-domain-cells = <1>; + #clock-cells = <0>; };
The HSIO blk-ctrl has a internal PLL, which can be used as a reference clock for the PCIe PHY. Add clock-cells to the binding to allow the driver to expose this PLL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ 1 file changed, 4 insertions(+)