| Message ID | 20221213232207.113607-3-marijn.suijten@somainline.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: DSC Electric Boogaloo for sm8[12]50 | expand |
On 14/12/2022 01:22, Marijn Suijten wrote: > These blocks on CTL V1 support setting a PINGPONG idx to send pixel > output to. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 23 ++++++++++++++----- > 1 file changed, 17 insertions(+), 6 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 12/13/2022 3:22 PM, Marijn Suijten wrote: > These blocks on CTL V1 support setting a PINGPONG idx to send pixel > output to. > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 23 ++++++++++++++----- > 1 file changed, 17 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 318f0b4dbf6e..114ad8ca4554 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -1566,18 +1566,25 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > /************************************************************* > * DSC sub blocks config > *************************************************************/ > -#define DSC_BLK(_name, _id, _base) \ > +#define DSC_BLK(_name, _id, _base, _features) \ > {\ > .name = _name, .id = _id, \ > .base = _base, .len = 0x140, \ > - .features = 0, \ > + .features = _features, \ > } > > static struct dpu_dsc_cfg sdm845_dsc[] = { > - DSC_BLK("dsc_0", DSC_0, 0x80000), > - DSC_BLK("dsc_1", DSC_1, 0x80400), > - DSC_BLK("dsc_2", DSC_2, 0x80800), > - DSC_BLK("dsc_3", DSC_3, 0x80c00), > + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), > + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), > + DSC_BLK("dsc_2", DSC_2, 0x80800, 0), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), > +}; > + > +static struct dpu_dsc_cfg sm8150_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), > }; > > /************************************************************* > @@ -2474,6 +2481,8 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { > .mixer = sm8150_lm, > .dspp_count = ARRAY_SIZE(sm8150_dspp), > .dspp = sm8150_dspp, > + .dsc_count = ARRAY_SIZE(sm8150_dsc), > + .dsc = sm8150_dsc, > .pingpong_count = ARRAY_SIZE(sm8150_pp), > .pingpong = sm8150_pp, > .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), > @@ -2524,6 +2533,8 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mixer = sm8150_lm, > .dspp_count = ARRAY_SIZE(sm8150_dspp), > .dspp = sm8150_dspp, > + .dsc_count = ARRAY_SIZE(sm8150_dsc), > + .dsc = sm8150_dsc, > .pingpong_count = ARRAY_SIZE(sm8150_pp), > .pingpong = sm8150_pp, > .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 318f0b4dbf6e..114ad8ca4554 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1566,18 +1566,25 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { /************************************************************* * DSC sub blocks config *************************************************************/ -#define DSC_BLK(_name, _id, _base) \ +#define DSC_BLK(_name, _id, _base, _features) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0x140, \ - .features = 0, \ + .features = _features, \ } static struct dpu_dsc_cfg sdm845_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000), - DSC_BLK("dsc_1", DSC_1, 0x80400), - DSC_BLK("dsc_2", DSC_2, 0x80800), - DSC_BLK("dsc_3", DSC_3, 0x80c00), + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), + DSC_BLK("dsc_2", DSC_2, 0x80800, 0), + DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), +}; + +static struct dpu_dsc_cfg sm8150_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), }; /************************************************************* @@ -2474,6 +2481,8 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { .mixer = sm8150_lm, .dspp_count = ARRAY_SIZE(sm8150_dspp), .dspp = sm8150_dspp, + .dsc_count = ARRAY_SIZE(sm8150_dsc), + .dsc = sm8150_dsc, .pingpong_count = ARRAY_SIZE(sm8150_pp), .pingpong = sm8150_pp, .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), @@ -2524,6 +2533,8 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { .mixer = sm8150_lm, .dspp_count = ARRAY_SIZE(sm8150_dspp), .dspp = sm8150_dspp, + .dsc_count = ARRAY_SIZE(sm8150_dsc), + .dsc = sm8150_dsc, .pingpong_count = ARRAY_SIZE(sm8150_pp), .pingpong = sm8150_pp, .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
These blocks on CTL V1 support setting a PINGPONG idx to send pixel output to. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-)