| Message ID | 20221216073141.3289309-2-milkfafa@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/nuvoton: Add NPCM memory controller driver | expand |
On 16/12/2022 08:31, Marvin Lin wrote: > Add node for memory controller present on Nuvoton NPCM SoCs. The > memory controller supports single bit error correction and double bit > error detection. > > Signed-off-by: Marvin Lin <milkfafa@gmail.com> Use subject prefixes matching the subsystem (git log --oneline -- ...). It's "ARM:" > --- > arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > Best regards, Krzysztof
Hi Krzysztof, > Use subject prefixes matching the subsystem (git log --oneline -- ...). > > It's "ARM:" Will correct the subject prefixes in next patch. Thanks for the review. Regards, Marvin
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index c7b5ef15b716..d875e8ac1e09 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -179,6 +179,13 @@ fiux: spi@fb001000 { status = "disabled"; }; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0xf0824000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>;
Add node for memory controller present on Nuvoton NPCM SoCs. The memory controller supports single bit error correction and double bit error detection. Signed-off-by: Marvin Lin <milkfafa@gmail.com> --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)