| Message ID | 20221213071640.3038853-1-Vsujithkumar.Reddy@amd.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | b5ba646142195d63dd1aae69bc15457fca5aeb78 |
| Headers | show |
| Series | ASoC: SOF: amd: Enable cache for AMD Rembrandt platform | expand |
On Tue, 13 Dec 2022 12:46:37 +0530, V sujith kumar Reddy wrote: > Enable DSP cache for ACP memory > > Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: SOF: amd: Enable cache for AMD Rembrandt platform commit: b5ba646142195d63dd1aae69bc15457fca5aeb78 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp-offset.h index de5726251dc6..920155dee819 100644 --- a/sound/soc/sof/amd/acp-dsp-offset.h +++ b/sound/soc/sof/amd/acp-dsp-offset.h @@ -85,4 +85,8 @@ #define ACP_SCRATCH_REG_0 0x10000 #define ACP6X_DSP_FUSION_RUNSTALL 0x0644 + +/* Cache window registers */ +#define ACP_DSP0_CACHE_OFFSET0 0x0420 +#define ACP_DSP0_CACHE_SIZE0 0x0424 #endif diff --git a/sound/soc/sof/amd/acp-loader.c b/sound/soc/sof/amd/acp-loader.c index 090c8b18c83c..a4bce5a3ae48 100644 --- a/sound/soc/sof/amd/acp-loader.c +++ b/sound/soc/sof/amd/acp-loader.c @@ -151,6 +151,7 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) { struct pci_dev *pci = to_pci_dev(sdev->dev); + const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); struct acp_dev_data *adata; unsigned int src_addr, size_fw; u32 page_count, dma_size; @@ -183,6 +184,12 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) if (ret < 0) dev_err(sdev->dev, "acp dma transfer status: %d\n", ret); + if (desc->rev > 3) { + /* Cache Window enable */ + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_OFFSET0, desc->sram_pte_offset); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_SIZE0, SRAM1_SIZE | BIT(31)); + } + /* Free memory once DMA is complete */ dma_size = (PAGE_ALIGN(sdev->basefw.fw->size) >> PAGE_SHIFT) * ACP_PAGE_SIZE; dma_free_coherent(&pci->dev, dma_size, adata->bin_buf, adata->sha_dma_addr); diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 09e16ef8afa0..4314094a97fd 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -72,6 +72,8 @@ #define EXCEPT_MAX_HDR_SIZE 0x400 #define AMD_STACK_DUMP_SIZE 32 +#define SRAM1_SIZE 0x13A000 + enum clock_source { ACP_CLOCK_96M = 0, ACP_CLOCK_48M,
Enable DSP cache for ACP memory Signed-off-by: V sujith kumar Reddy <Vsujithkumar.Reddy@amd.com> --- sound/soc/sof/amd/acp-dsp-offset.h | 4 ++++ sound/soc/sof/amd/acp-loader.c | 7 +++++++ sound/soc/sof/amd/acp.h | 2 ++ 3 files changed, 13 insertions(+)