| Message ID | 20230113103759.327698-6-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add the PowerQUICC audio support using the QMC | expand |
On 13/01/2023 11:37, Herve Codina wrote: > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > --- > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ > 1 file changed, 164 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > new file mode 100644 > index 000000000000..3ec52f1635c8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > @@ -0,0 +1,164 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina <herve.codina@bootlin.com> > + > +description: | > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within > + one serial controller using the same TDM physical interface routed from > + TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to the TSA > + > + fsl,tsa-cell-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [1, 2, 3] > + description: | > + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 Is this used as argument to tsa? If so, this should be part of fsl,tsa property, just like we do for all syscon-like phandles. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#chan-cells': > + const: 1 > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: Operational mode You still need to explain what do transparent and hdlc mean. > + Best regards, Krzysztof
Hi Krzysztof, On Tue, 17 Jan 2023 12:31:09 +0100 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 13/01/2023 11:37, Herve Codina wrote: > > Add support for the QMC (QUICC Multichannel Controller) > > available in some PowerQUICC SoC such as MPC885 or MPC866. > > > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > > --- > > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ > > 1 file changed, 164 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > new file mode 100644 > > index 000000000000..3ec52f1635c8 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > @@ -0,0 +1,164 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > > + > > +maintainers: > > + - Herve Codina <herve.codina@bootlin.com> > > + > > +description: | > > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within > > + one serial controller using the same TDM physical interface routed from > > + TSA. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - fsl,mpc885-scc-qmc > > + - fsl,mpc866-scc-qmc > > + - const: fsl,cpm1-scc-qmc > > + > > + reg: > > + items: > > + - description: SCC (Serial communication controller) register base > > + - description: SCC parameter ram base > > + - description: Dual port ram base > > + > > + reg-names: > > + items: > > + - const: scc_regs > > + - const: scc_pram > > + - const: dpram > > + > > + interrupts: > > + maxItems: 1 > > + description: SCC interrupt line in the CPM interrupt controller > > + > > + fsl,tsa: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the TSA > > + > > + fsl,tsa-cell-id: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [1, 2, 3] > > + description: | > > + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > > + - 1: SCC2 > > + - 2: SCC3 > > + - 3: SCC4 > > Is this used as argument to tsa? If so, this should be part of fsl,tsa > property, just like we do for all syscon-like phandles. Yes, indeed. I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number pair (the phandle to TSA node and the TSA cell id to use) > > > + > > + '#address-cells': > > + const: 1 > > + > > + '#size-cells': > > + const: 0 > > + > > + '#chan-cells': > > + const: 1 > > + > > +patternProperties: > > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > > + description: > > + A channel managed by this controller > > + type: object > > + > > + properties: > > + reg: > > + minimum: 0 > > + maximum: 63 > > + description: > > + The channel number > > + > > + fsl,mode: > > + $ref: /schemas/types.yaml#/definitions/string > > + enum: [transparent, hdlc] > > + default: transparent > > + description: Operational mode > > You still need to explain what do transparent and hdlc mean. Oups, my bad (already mentioned in the previous version review). Also, I will rename the property to 'fsl,operational-mode' to be more precise than just 'fsl,mode' > > > + > > > Best regards, > Krzysztof > Thanks for the review, Hervé
On 24/01/2023 10:42, Herve Codina wrote: > Hi Krzysztof, > > On Tue, 17 Jan 2023 12:31:09 +0100 > Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > >> On 13/01/2023 11:37, Herve Codina wrote: >>> Add support for the QMC (QUICC Multichannel Controller) >>> available in some PowerQUICC SoC such as MPC885 or MPC866. >>> >>> Signed-off-by: Herve Codina <herve.codina@bootlin.com> >>> --- >>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ >>> 1 file changed, 164 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>> new file mode 100644 >>> index 000000000000..3ec52f1635c8 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>> @@ -0,0 +1,164 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) >>> + >>> +maintainers: >>> + - Herve Codina <herve.codina@bootlin.com> >>> + >>> +description: | >>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within >>> + one serial controller using the same TDM physical interface routed from >>> + TSA. >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - fsl,mpc885-scc-qmc >>> + - fsl,mpc866-scc-qmc >>> + - const: fsl,cpm1-scc-qmc >>> + >>> + reg: >>> + items: >>> + - description: SCC (Serial communication controller) register base >>> + - description: SCC parameter ram base >>> + - description: Dual port ram base >>> + >>> + reg-names: >>> + items: >>> + - const: scc_regs >>> + - const: scc_pram >>> + - const: dpram >>> + >>> + interrupts: >>> + maxItems: 1 >>> + description: SCC interrupt line in the CPM interrupt controller >>> + >>> + fsl,tsa: >>> + $ref: /schemas/types.yaml#/definitions/phandle >>> + description: phandle to the TSA >>> + >>> + fsl,tsa-cell-id: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: [1, 2, 3] >>> + description: | >>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) >>> + - 1: SCC2 >>> + - 2: SCC3 >>> + - 3: SCC4 >> >> Is this used as argument to tsa? If so, this should be part of fsl,tsa >> property, just like we do for all syscon-like phandles. > > Yes, indeed. > I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number > pair (the phandle to TSA node and the TSA cell id to use) Move to fsl,tsa, not from. Best regards, Krzysztof
On Tue, 24 Jan 2023 11:02:52 +0100 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 24/01/2023 10:42, Herve Codina wrote: > > Hi Krzysztof, > > > > On Tue, 17 Jan 2023 12:31:09 +0100 > > Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > > >> On 13/01/2023 11:37, Herve Codina wrote: > >>> Add support for the QMC (QUICC Multichannel Controller) > >>> available in some PowerQUICC SoC such as MPC885 or MPC866. > >>> > >>> Signed-off-by: Herve Codina <herve.codina@bootlin.com> > >>> --- > >>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ > >>> 1 file changed, 164 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > >>> new file mode 100644 > >>> index 000000000000..3ec52f1635c8 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > >>> @@ -0,0 +1,164 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > >>> + > >>> +maintainers: > >>> + - Herve Codina <herve.codina@bootlin.com> > >>> + > >>> +description: | > >>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within > >>> + one serial controller using the same TDM physical interface routed from > >>> + TSA. > >>> + > >>> +properties: > >>> + compatible: > >>> + items: > >>> + - enum: > >>> + - fsl,mpc885-scc-qmc > >>> + - fsl,mpc866-scc-qmc > >>> + - const: fsl,cpm1-scc-qmc > >>> + > >>> + reg: > >>> + items: > >>> + - description: SCC (Serial communication controller) register base > >>> + - description: SCC parameter ram base > >>> + - description: Dual port ram base > >>> + > >>> + reg-names: > >>> + items: > >>> + - const: scc_regs > >>> + - const: scc_pram > >>> + - const: dpram > >>> + > >>> + interrupts: > >>> + maxItems: 1 > >>> + description: SCC interrupt line in the CPM interrupt controller > >>> + > >>> + fsl,tsa: > >>> + $ref: /schemas/types.yaml#/definitions/phandle > >>> + description: phandle to the TSA > >>> + > >>> + fsl,tsa-cell-id: > >>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>> + enum: [1, 2, 3] > >>> + description: | > >>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > >>> + - 1: SCC2 > >>> + - 2: SCC3 > >>> + - 3: SCC4 > >> > >> Is this used as argument to tsa? If so, this should be part of fsl,tsa > >> property, just like we do for all syscon-like phandles. > > > > Yes, indeed. > > I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number > > pair (the phandle to TSA node and the TSA cell id to use) > > Move to fsl,tsa, not from. Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: fsl,tsa-cell: $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to TSA node - enum: [1, 2, 3] description: | TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) - 1: SCC2 - 2: SCC3 - 3: SCC4 description: Should be a phandle/number pair. The phandle to TSA node and the TSA cell ID to use. Is that what you were thinking about ? Best regards, Hervé
On 24/01/2023 12:23, Herve Codina wrote: > On Tue, 24 Jan 2023 11:02:52 +0100 > Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > >> On 24/01/2023 10:42, Herve Codina wrote: >>> Hi Krzysztof, >>> >>> On Tue, 17 Jan 2023 12:31:09 +0100 >>> Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: >>> >>>> On 13/01/2023 11:37, Herve Codina wrote: >>>>> Add support for the QMC (QUICC Multichannel Controller) >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866. >>>>> >>>>> Signed-off-by: Herve Codina <herve.codina@bootlin.com> >>>>> --- >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ >>>>> 1 file changed, 164 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..3ec52f1635c8 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> @@ -0,0 +1,164 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) >>>>> + >>>>> +maintainers: >>>>> + - Herve Codina <herve.codina@bootlin.com> >>>>> + >>>>> +description: | >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within >>>>> + one serial controller using the same TDM physical interface routed from >>>>> + TSA. >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + items: >>>>> + - enum: >>>>> + - fsl,mpc885-scc-qmc >>>>> + - fsl,mpc866-scc-qmc >>>>> + - const: fsl,cpm1-scc-qmc >>>>> + >>>>> + reg: >>>>> + items: >>>>> + - description: SCC (Serial communication controller) register base >>>>> + - description: SCC parameter ram base >>>>> + - description: Dual port ram base >>>>> + >>>>> + reg-names: >>>>> + items: >>>>> + - const: scc_regs >>>>> + - const: scc_pram >>>>> + - const: dpram >>>>> + >>>>> + interrupts: >>>>> + maxItems: 1 >>>>> + description: SCC interrupt line in the CPM interrupt controller >>>>> + >>>>> + fsl,tsa: >>>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>>> + description: phandle to the TSA >>>>> + >>>>> + fsl,tsa-cell-id: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: [1, 2, 3] >>>>> + description: | >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) >>>>> + - 1: SCC2 >>>>> + - 2: SCC3 >>>>> + - 3: SCC4 >>>> >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa >>>> property, just like we do for all syscon-like phandles. >>> >>> Yes, indeed. >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number >>> pair (the phandle to TSA node and the TSA cell id to use) >> >> Move to fsl,tsa, not from. > > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: > fsl,tsa-cell: > $ref: /schemas/types.yaml#/definitions/phandle-array > items: > - items: > - description: phandle to TSA node > - enum: [1, 2, 3] > description: | > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > - 1: SCC2 > - 2: SCC3 > - 3: SCC4 > description: > Should be a phandle/number pair. The phandle to TSA node and the TSA > cell ID to use. > > Is that what you were thinking about ? Yes, except again, so third time, why calling this "cell"? Move it to fsl,tsa. Best regards, Krzysztof
On Tue, 24 Jan 2023 13:24:48 +0100 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > On 24/01/2023 12:23, Herve Codina wrote: > > On Tue, 24 Jan 2023 11:02:52 +0100 > > Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > > >> On 24/01/2023 10:42, Herve Codina wrote: > >>> Hi Krzysztof, > >>> > >>> On Tue, 17 Jan 2023 12:31:09 +0100 > >>> Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > >>> > >>>> On 13/01/2023 11:37, Herve Codina wrote: > >>>>> Add support for the QMC (QUICC Multichannel Controller) > >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866. > >>>>> > >>>>> Signed-off-by: Herve Codina <herve.codina@bootlin.com> > >>>>> --- > >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ > >>>>> 1 file changed, 164 insertions(+) > >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > >>>>> > >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > >>>>> new file mode 100644 > >>>>> index 000000000000..3ec52f1635c8 > >>>>> --- /dev/null > >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > >>>>> @@ -0,0 +1,164 @@ > >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>>>> +%YAML 1.2 > >>>>> +--- > >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>>>> + > >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > >>>>> + > >>>>> +maintainers: > >>>>> + - Herve Codina <herve.codina@bootlin.com> > >>>>> + > >>>>> +description: | > >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within > >>>>> + one serial controller using the same TDM physical interface routed from > >>>>> + TSA. > >>>>> + > >>>>> +properties: > >>>>> + compatible: > >>>>> + items: > >>>>> + - enum: > >>>>> + - fsl,mpc885-scc-qmc > >>>>> + - fsl,mpc866-scc-qmc > >>>>> + - const: fsl,cpm1-scc-qmc > >>>>> + > >>>>> + reg: > >>>>> + items: > >>>>> + - description: SCC (Serial communication controller) register base > >>>>> + - description: SCC parameter ram base > >>>>> + - description: Dual port ram base > >>>>> + > >>>>> + reg-names: > >>>>> + items: > >>>>> + - const: scc_regs > >>>>> + - const: scc_pram > >>>>> + - const: dpram > >>>>> + > >>>>> + interrupts: > >>>>> + maxItems: 1 > >>>>> + description: SCC interrupt line in the CPM interrupt controller > >>>>> + > >>>>> + fsl,tsa: > >>>>> + $ref: /schemas/types.yaml#/definitions/phandle > >>>>> + description: phandle to the TSA > >>>>> + > >>>>> + fsl,tsa-cell-id: > >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>>>> + enum: [1, 2, 3] > >>>>> + description: | > >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > >>>>> + - 1: SCC2 > >>>>> + - 2: SCC3 > >>>>> + - 3: SCC4 > >>>> > >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa > >>>> property, just like we do for all syscon-like phandles. > >>> > >>> Yes, indeed. > >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number > >>> pair (the phandle to TSA node and the TSA cell id to use) > >> > >> Move to fsl,tsa, not from. > > > > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: > > fsl,tsa-cell: > > $ref: /schemas/types.yaml#/definitions/phandle-array > > items: > > - items: > > - description: phandle to TSA node > > - enum: [1, 2, 3] > > description: | > > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > > - 1: SCC2 > > - 2: SCC3 > > - 3: SCC4 > > description: > > Should be a phandle/number pair. The phandle to TSA node and the TSA > > cell ID to use. > > > > Is that what you were thinking about ? > > Yes, except again, so third time, why calling this "cell"? Move it to > fsl,tsa. > Why calling this "cell" ? Just because we reference a "cell" using the TSA cell ID inside TSA and not the TSA itself. Maybe the problem is the term "cell" as it is not the DT definition of "cell" but the source/destination of the TSA routing. TSA can route data from/to some "serial controller". These serial controllers are : - SCC (Serial Communication Controller) - SMC (Serial Management Controller) - UCC (Unified Communication Controller) Only SCCs are handled here. Maybe the term "serial" makes more sense which will lead to fsl,tsa-serial = <&tsa, SCC4>; Best regards, Hervé
On 24/01/2023 15:15, Herve Codina wrote: >>> Is that what you were thinking about ? >> >> Yes, except again, so third time, why calling this "cell"? Move it to >> fsl,tsa. >> > > Why calling this "cell" ? Just because we reference a "cell" using the TSA > cell ID inside TSA and not the TSA itself. > > Maybe the problem is the term "cell" as it is not the DT definition of > "cell" but the source/destination of the TSA routing. > > TSA can route data from/to some "serial controller". > These serial controllers are : > - SCC (Serial Communication Controller) > - SMC (Serial Management Controller) > - UCC (Unified Communication Controller) > > Only SCCs are handled here. > > Maybe the term "serial" makes more sense which will lead to > fsl,tsa-serial = <&tsa, SCC4>; Yes, that's better. Thanks. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml new file mode 100644 index 000000000000..3ec52f1635c8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: | + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within + one serial controller using the same TDM physical interface routed from + TSA. + +properties: + compatible: + items: + - enum: + - fsl,mpc885-scc-qmc + - fsl,mpc866-scc-qmc + - const: fsl,cpm1-scc-qmc + + reg: + items: + - description: SCC (Serial communication controller) register base + - description: SCC parameter ram base + - description: Dual port ram base + + reg-names: + items: + - const: scc_regs + - const: scc_pram + - const: dpram + + interrupts: + maxItems: 1 + description: SCC interrupt line in the CPM interrupt controller + + fsl,tsa: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the TSA + + fsl,tsa-cell-id: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: | + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) + - 1: SCC2 + - 2: SCC3 + - 3: SCC4 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#chan-cells': + const: 1 + +patternProperties: + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': + description: + A channel managed by this controller + type: object + + properties: + reg: + minimum: 0 + maximum: 63 + description: + The channel number + + fsl,mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [transparent, hdlc] + default: transparent + description: Operational mode + + fsl,reverse-data: + $ref: /schemas/types.yaml#/definitions/flag + description: + The bit order as seen on the channels is reversed, + transmitting/receiving the MSB of each octet first. + This flag is used only in 'transparent' mode. + + fsl,tx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Tx time-slots within the Tx time-slots routed + by the TSA to this cell. + + fsl,rx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Rx time-slots within the Rx time-slots routed + by the TSA to this cell. + + required: + - reg + - fsl,tx-ts-mask + - fsl,rx-ts-mask + +required: + - compatible + - reg + - reg-names + - interrupts + - fsl,tsa + - fsl,tsa-cell-id + - '#address-cells' + - '#size-cells' + - '#chan-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/fsl,tsa.h> + + qmc@a60 { + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; + reg = <0xa60 0x20>, + <0x3f00 0xc0>, + <0x2000 0x1000>; + reg-names = "scc_regs", "scc_pram", "dpram"; + interrupts = <27>; + interrupt-parent = <&CPM_PIC>; + + #address-cells = <1>; + #size-cells = <0>; + #chan-cells = <1>; + + fsl,tsa = <&tsa>; + fsl,tsa-cell-id = <FSL_CPM_TSA_SCC4>; + + channel@16 { + /* Ch16 : First 4 even TS from all routed from TSA */ + reg = <16>; + fsl,mode = "transparent"; + fsl,reverse-data; + fsl,tx-ts-mask = <0x00000000 0x000000aa>; + fsl,rx-ts-mask = <0x00000000 0x000000aa>; + }; + + channel@17 { + /* Ch17 : First 4 odd TS from all routed from TSA */ + reg = <17>; + fsl,mode = "transparent"; + fsl,reverse-data; + fsl,tx-ts-mask = <0x00000000 0x00000055>; + fsl,rx-ts-mask = <0x00000000 0x00000055>; + }; + + channel@19 { + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ + reg = <19>; + fsl,mode = "hdlc"; + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; + }; + };
Add support for the QMC (QUICC Multichannel Controller) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml