| Message ID | 20230118061701.30047-7-yanhong.wang@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add Ethernet driver for StarFive JH7110 SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On 18/01/2023 07:17, Yanhong Wang wrote: > Add JH7110 ethernet device node to support gmac driver for the JH7110 > RISC-V SoC. > > Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ > 1 file changed, 93 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index c22e8f1d2640..c6de6e3b1a25 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -433,5 +433,98 @@ > reg-shift = <2>; > status = "disabled"; > }; > + > + stmmac_axi_setup: stmmac-axi-config { Why your bindings example is different? Were the bindings tested? Ahh, no they were not... Can you send only tested patches? Was this tested? > + snps,lpi_en; > + snps,wr_osr_lmt = <4>; > + snps,rd_osr_lmt = <4>; > + snps,blen = <256 128 64 32 0 0 0>; > + }; > + Best regards, Krzysztof
On 2023/1/18 23:51, Krzysztof Kozlowski wrote: > On 18/01/2023 07:17, Yanhong Wang wrote: >> Add JH7110 ethernet device node to support gmac driver for the JH7110 >> RISC-V SoC. >> >> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> >> --- >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ >> 1 file changed, 93 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> index c22e8f1d2640..c6de6e3b1a25 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -433,5 +433,98 @@ >> reg-shift = <2>; >> status = "disabled"; >> }; >> + >> + stmmac_axi_setup: stmmac-axi-config { > > Why your bindings example is different? > There are two gmacs on the StarFive VF2 board, and the two gmacs use the same configuration on axi, so the stmmac_axi_setup is independent, which is different from the bindings example. > Were the bindings tested? Ahh, no they were not... Can you send only > tested patches? > > Was this tested? > Yes, the bindings have been tested on the StarFive VF2 board and work normally. >> + snps,lpi_en; >> + snps,wr_osr_lmt = <4>; >> + snps,rd_osr_lmt = <4>; >> + snps,blen = <256 128 64 32 0 0 0>; >> + }; >> + > > Best regards, > Krzysztof >
On 03/02/2023 04:14, yanhong wang wrote: > > > On 2023/1/18 23:51, Krzysztof Kozlowski wrote: >> On 18/01/2023 07:17, Yanhong Wang wrote: >>> Add JH7110 ethernet device node to support gmac driver for the JH7110 >>> RISC-V SoC. >>> >>> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> >>> --- >>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ >>> 1 file changed, 93 insertions(+) >>> >>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >>> index c22e8f1d2640..c6de6e3b1a25 100644 >>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >>> @@ -433,5 +433,98 @@ >>> reg-shift = <2>; >>> status = "disabled"; >>> }; >>> + >>> + stmmac_axi_setup: stmmac-axi-config { >> >> Why your bindings example is different? >> > > There are two gmacs on the StarFive VF2 board, and the two > gmacs use the same configuration on axi, so the > stmmac_axi_setup is independent, which is different > from the bindings example. > > >> Were the bindings tested? Ahh, no they were not... Can you send only >> tested patches? >> >> Was this tested? >> > Yes, the bindings have been tested on the StarFive VF2 board and work normally. Then please tell me how did you test the bindings on the board? How is it even possible and how the board is related to bindings? As you could easily see from Rob's reply they fail, so I have doubts that they were tested. If you still claim they were - please paste the output from testing command. Best regards, Krzysztof
On 2023/2/3 15:09, Krzysztof Kozlowski wrote: > On 03/02/2023 04:14, yanhong wang wrote: >> >> >> On 2023/1/18 23:51, Krzysztof Kozlowski wrote: >>> On 18/01/2023 07:17, Yanhong Wang wrote: >>>> Add JH7110 ethernet device node to support gmac driver for the JH7110 >>>> RISC-V SoC. >>>> >>>> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> >>>> --- >>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ >>>> 1 file changed, 93 insertions(+) >>>> >>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >>>> index c22e8f1d2640..c6de6e3b1a25 100644 >>>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >>>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >>>> @@ -433,5 +433,98 @@ >>>> reg-shift = <2>; >>>> status = "disabled"; >>>> }; >>>> + >>>> + stmmac_axi_setup: stmmac-axi-config { >>> >>> Why your bindings example is different? >>> >> >> There are two gmacs on the StarFive VF2 board, and the two >> gmacs use the same configuration on axi, so the >> stmmac_axi_setup is independent, which is different >> from the bindings example. >> >> >>> Were the bindings tested? Ahh, no they were not... Can you send only >>> tested patches? >>> >>> Was this tested? >>> >> Yes, the bindings have been tested on the StarFive VF2 board and work normally. > > Then please tell me how did you test the bindings on the board? How is > it even possible and how the board is related to bindings? As you could > easily see from Rob's reply they fail, so I have doubts that they were > tested. If you still claim they were - please paste the output from > testing command. > Sorry, I didn't check all the bindings, only the modified ones, the command used is as follows: "make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/snps,dwmac.yaml" "make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml" > > Best regards, > Krzysztof >
On 03/02/2023 08:40, yanhong wang wrote: >> > > Sorry, I didn't check all the bindings, only the modified ones, the command > used is as follows: > "make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/snps,dwmac.yaml" > "make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml" That's good actually, except that you change binding used by others, so you affect other files. However in this DTS you will have now warnings (dtbs_check with simple-bus or dtbs W=1) because of using non-MMIO node in your soc-bus. The stmmac-axi-config probably should be moved outside of soc node. Or you keep two of them - one in each ethernet node. Best regards, Krzysztof
On 2023/2/3 15:56, Krzysztof Kozlowski wrote: > On 03/02/2023 08:40, yanhong wang wrote: >>> >> >> Sorry, I didn't check all the bindings, only the modified ones, the command >> used is as follows: >> "make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/snps,dwmac.yaml" >> "make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml" > > That's good actually, except that you change binding used by others, so > you affect other files. > > However in this DTS you will have now warnings (dtbs_check with > simple-bus or dtbs W=1) because of using non-MMIO node in your soc-bus. > The stmmac-axi-config probably should be moved outside of soc node. Or > you keep two of them - one in each ethernet node. > Thanks. The stmmac-axi-config probably will be moved outside of soc node in the next version. > Best regards, > Krzysztof >
On Wed, 18 Jan 2023 at 07:19, Yanhong Wang <yanhong.wang@starfivetech.com> wrote: > Add JH7110 ethernet device node to support gmac driver for the JH7110 > RISC-V SoC. > > Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ > 1 file changed, 93 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index c22e8f1d2640..c6de6e3b1a25 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -433,5 +433,98 @@ > reg-shift = <2>; > status = "disabled"; > }; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,lpi_en; > + snps,wr_osr_lmt = <4>; > + snps,rd_osr_lmt = <4>; > + snps,blen = <256 128 64 32 0 0 0>; > + }; > + > + gmac0: ethernet@16030000 { > + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; > + reg = <0x0 0x16030000 0x0 0x10000>; > + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, > + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, > + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, > + <&aoncrg JH7110_AONCLK_GMAC0_TX>, The gmac0_tx clock is a mux that takes either the gmac0_gtxclk or rmii_rtx as parent. However it is then followed by an inverter that optionally inverts the clock, gmac0_tx_inv. I'm guessing this optionally inverted signal is what is actually used (otherwise why would the inverter exist), so I think this clock is what should be claimed here. Eg. <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, Right now it works only because the inverted signal can't be gated (turned off) even when it's not claimed by any driver. > + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>, > + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; Here the gmac0_gtxclk clock is the parent of the gmac0_gtxc, so claiming the gmac0_gtxc should be enough. Since the gmac0_gtxc is just a gate it should have the CLK_SET_RATE_PARENT flag set, so the driver can just change the rate of the child and it should propagate to the parent. In short I think claiming only the gmac0_gtxc clock should be enough here. > + clock-names = "stmmaceth", "pclk", "ptp_ref", > + "tx", "gtxc", "gtx"; > + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, > + <&aoncrg JH7110_AONRST_GMAC0_AHB>; > + reset-names = "stmmaceth", "ahb"; > + interrupts = <7>, <6>, <5>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > + phy-mode = "rgmii-id"; > + snps,multicast-filter-bins = <64>; > + snps,perfect-filter-entries = <8>; > + rx-fifo-depth = <2048>; > + tx-fifo-depth = <2048>; > + snps,fixed-burst; > + snps,no-pbl-x8; > + snps,force_thresh_dma_mode; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,tso; > + snps,en-tx-lpi-clockgating; > + snps,txpbl = <16>; > + snps,rxpbl = <16>; > + status = "disabled"; > + phy-handle = <&phy0>; > + > + mdio0: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + phy0: ethernet-phy@0 { > + reg = <0>; > + }; > + }; > + }; > + > + gmac1: ethernet@16040000 { > + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; > + reg = <0x0 0x16040000 0x0 0x10000>; > + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, > + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, > + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, > + <&syscrg JH7110_SYSCLK_GMAC1_TX>, > + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>, > + <&syscrg JH7110_SYSCLK_GMAC1_GTXCLK>; > + clock-names = "stmmaceth", "pclk", "ptp_ref", > + "tx", "gtxc", "gtx"; > + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, > + <&syscrg JH7110_SYSRST_GMAC1_AHB>; > + reset-names = "stmmaceth", "ahb"; > + interrupts = <78>, <77>, <76>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > + phy-mode = "rgmii-id"; > + snps,multicast-filter-bins = <64>; > + snps,perfect-filter-entries = <8>; > + rx-fifo-depth = <2048>; > + tx-fifo-depth = <2048>; > + snps,fixed-burst; > + snps,no-pbl-x8; > + snps,force_thresh_dma_mode; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,tso; > + snps,en-tx-lpi-clockgating; > + snps,txpbl = <16>; > + snps,rxpbl = <16>; > + status = "disabled"; > + phy-handle = <&phy1>; > + > + mdio1: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dwmac-mdio"; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + }; > + }; > + }; > }; > }; > -- > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Mon, 20 Feb 2023 at 15:22, Emil Renner Berthing <emil.renner.berthing@canonical.com> wrote: > On Wed, 18 Jan 2023 at 07:19, Yanhong Wang > <yanhong.wang@starfivetech.com> wrote: > > Add JH7110 ethernet device node to support gmac driver for the JH7110 > > RISC-V SoC. > > > > Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> > > --- > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ > > 1 file changed, 93 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > index c22e8f1d2640..c6de6e3b1a25 100644 > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > @@ -433,5 +433,98 @@ > > reg-shift = <2>; > > status = "disabled"; > > }; > > + > > + stmmac_axi_setup: stmmac-axi-config { > > + snps,lpi_en; > > + snps,wr_osr_lmt = <4>; > > + snps,rd_osr_lmt = <4>; > > + snps,blen = <256 128 64 32 0 0 0>; > > + }; > > + > > + gmac0: ethernet@16030000 { > > + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; > > + reg = <0x0 0x16030000 0x0 0x10000>; > > + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, > > + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, > > + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, > > + <&aoncrg JH7110_AONCLK_GMAC0_TX>, > > The gmac0_tx clock is a mux that takes either the gmac0_gtxclk or > rmii_rtx as parent. However it is then followed by an inverter that > optionally inverts the clock, gmac0_tx_inv. I'm guessing this > optionally inverted signal is what is actually used (otherwise why > would the inverter exist), so I think this clock is what should be > claimed here. Eg. > <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, > > Right now it works only because the inverted signal can't be gated > (turned off) even when it's not claimed by any driver. > > > + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>, > > + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; > > Here the gmac0_gtxclk clock is the parent of the gmac0_gtxc, so > claiming the gmac0_gtxc should be enough. Since the gmac0_gtxc is just > a gate it should have the CLK_SET_RATE_PARENT flag set, so the driver > can just change the rate of the child and it should propagate to the > parent. In short I think claiming only the gmac0_gtxc clock should be > enough here. Oh and just for completeness. This also goes for gmac1 below, and don't forget to update the yaml binding doc accordingly. > > + clock-names = "stmmaceth", "pclk", "ptp_ref", > > + "tx", "gtxc", "gtx"; > > + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, > > + <&aoncrg JH7110_AONRST_GMAC0_AHB>; > > + reset-names = "stmmaceth", "ahb"; > > + interrupts = <7>, <6>, <5>; > > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > > + phy-mode = "rgmii-id"; > > + snps,multicast-filter-bins = <64>; > > + snps,perfect-filter-entries = <8>; > > + rx-fifo-depth = <2048>; > > + tx-fifo-depth = <2048>; > > + snps,fixed-burst; > > + snps,no-pbl-x8; > > + snps,force_thresh_dma_mode; > > + snps,axi-config = <&stmmac_axi_setup>; > > + snps,tso; > > + snps,en-tx-lpi-clockgating; > > + snps,txpbl = <16>; > > + snps,rxpbl = <16>; > > + status = "disabled"; > > + phy-handle = <&phy0>; > > + > > + mdio0: mdio { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "snps,dwmac-mdio"; > > + > > + phy0: ethernet-phy@0 { > > + reg = <0>; > > + }; > > + }; > > + }; > > + > > + gmac1: ethernet@16040000 { > > + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; > > + reg = <0x0 0x16040000 0x0 0x10000>; > > + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, > > + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, > > + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, > > + <&syscrg JH7110_SYSCLK_GMAC1_TX>, > > + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>, > > + <&syscrg JH7110_SYSCLK_GMAC1_GTXCLK>; > > + clock-names = "stmmaceth", "pclk", "ptp_ref", > > + "tx", "gtxc", "gtx"; > > + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, > > + <&syscrg JH7110_SYSRST_GMAC1_AHB>; > > + reset-names = "stmmaceth", "ahb"; > > + interrupts = <78>, <77>, <76>; > > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > > + phy-mode = "rgmii-id"; > > + snps,multicast-filter-bins = <64>; > > + snps,perfect-filter-entries = <8>; > > + rx-fifo-depth = <2048>; > > + tx-fifo-depth = <2048>; > > + snps,fixed-burst; > > + snps,no-pbl-x8; > > + snps,force_thresh_dma_mode; > > + snps,axi-config = <&stmmac_axi_setup>; > > + snps,tso; > > + snps,en-tx-lpi-clockgating; > > + snps,txpbl = <16>; > > + snps,rxpbl = <16>; > > + status = "disabled"; > > + phy-handle = <&phy1>; > > + > > + mdio1: mdio { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "snps,dwmac-mdio"; > > + > > + phy1: ethernet-phy@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > }; > > }; > > -- > > 2.17.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index c22e8f1d2640..c6de6e3b1a25 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -433,5 +433,98 @@ reg-shift = <2>; status = "disabled"; }; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <4>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + gmac0: ethernet@16030000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16030000 0x0 0x10000>; + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, + <&aoncrg JH7110_AONCLK_GMAC0_TX>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtxc", "gtx"; + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, + <&aoncrg JH7110_AONRST_GMAC0_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <7>, <6>, <5>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + phy-mode = "rgmii-id"; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <8>; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + phy-handle = <&phy0>; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + gmac1: ethernet@16040000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, + <&syscrg JH7110_SYSCLK_GMAC1_TX>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXCLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtxc", "gtx"; + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, + <&syscrg JH7110_SYSRST_GMAC1_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <78>, <77>, <76>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + phy-mode = "rgmii-id"; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <8>; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + phy-handle = <&phy1>; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; }; };
Add JH7110 ethernet device node to support gmac driver for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 93 ++++++++++++++++++++++++ 1 file changed, 93 insertions(+)