diff mbox series

[1/3] clk: vc5: Use `clamp()` to restrict PLL range

Message ID 20230114233500.3294789-1-lars@metafoo.de (mailing list archive)
State Accepted, archived
Headers show
Series [1/3] clk: vc5: Use `clamp()` to restrict PLL range | expand

Commit Message

Lars-Peter Clausen Jan. 14, 2023, 11:34 p.m. UTC
The VCO frequency needs to be within a certain range and the driver
enforces this.

Make use of the clamp macro to implement this instead of open-coding it.
This makes the code a bit shorter and also semanticly stronger.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/clk/clk-versaclock5.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

Comments

Luca Ceresoli Jan. 16, 2023, 8:15 a.m. UTC | #1
Hello Lars-Peter,

On Sat, 14 Jan 2023 15:34:58 -0800
Lars-Peter Clausen <lars@metafoo.de> wrote:

> The VCO frequency needs to be within a certain range and the driver
> enforces this.
> 
> Make use of the clamp macro to implement this instead of open-coding it.
> This makes the code a bit shorter and also semanticly stronger.
> 
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Stephen Boyd Jan. 18, 2023, 6:57 p.m. UTC | #2
Quoting Lars-Peter Clausen (2023-01-14 15:34:58)
> The VCO frequency needs to be within a certain range and the driver
> enforces this.
> 
> Make use of the clamp macro to implement this instead of open-coding it.
> This makes the code a bit shorter and also semanticly stronger.
> 
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index e9737969170e..54fee43d6564 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -449,10 +449,7 @@  static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 	u32 div_int;
 	u64 div_frc;
 
-	if (rate < VC5_PLL_VCO_MIN)
-		rate = VC5_PLL_VCO_MIN;
-	if (rate > VC5_PLL_VCO_MAX)
-		rate = VC5_PLL_VCO_MAX;
+	rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX);
 
 	/* Determine integer part, which is 12 bit wide */
 	div_int = rate / *parent_rate;