diff mbox series

[1/2] drm/i915/mtl: Add workarounds Wa_14017066071, Wa_14017654203

Message ID 20230120010639.3691331-1-radhakrishna.sripada@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915/mtl: Add workarounds Wa_14017066071, Wa_14017654203 | expand

Commit Message

Sripada, Radhakrishna Jan. 20, 2023, 1:06 a.m. UTC
This patch add the workaround to disable Sampler-OOO to avoid hang
during a benchmark.

Original Author: Madhumitha Tolakanhalli Pradeep
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
 2 files changed, 8 insertions(+)

Comments

Rodrigo Vivi Jan. 20, 2023, 10:47 a.m. UTC | #1
On Thu, Jan 19, 2023 at 05:06:38PM -0800, Radhakrishna Sripada wrote:
> This patch add the workaround to disable Sampler-OOO to avoid hang
> during a benchmark.
> 
> Original Author: Madhumitha Tolakanhalli Pradeep

This is not how we handle this. We keep her original authorship email
and signed-off.

> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4a4bab261e66..27b06ff380a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1145,6 +1145,7 @@
>  #define   ENABLE_SMALLPL			REG_BIT(15)
>  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
> +#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)
>  
>  #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>  #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 918a271447e2..c52c5f9ad9ce 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2332,6 +2332,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  		/* Wa_22014600077 */
>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> +
> +		/*
> +		 * Wa_14017066071: mtl-p/m[a0]
> +		 * Wa_14017654203: mtl-p/m[a0]
> +		 */
> +		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> +				 MTL_DISABLE_SAMPLER_SC_OOO);
>  	}
>  
>  	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -- 
> 2.34.1
>
Jani Nikula Jan. 24, 2023, 8:58 a.m. UTC | #2
On Fri, 20 Jan 2023, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Jan 19, 2023 at 05:06:38PM -0800, Radhakrishna Sripada wrote:
>> This patch add the workaround to disable Sampler-OOO to avoid hang
>> during a benchmark.
>> 
>> Original Author: Madhumitha Tolakanhalli Pradeep
>
> This is not how we handle this. We keep her original authorship email
> and signed-off.

Also, "This patch" is redundant, and once committed, just wrong.

>
>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>>  2 files changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 4a4bab261e66..27b06ff380a9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -1145,6 +1145,7 @@
>>  #define   ENABLE_SMALLPL			REG_BIT(15)
>>  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
>> +#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)
>>  
>>  #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
>>  #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 918a271447e2..c52c5f9ad9ce 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -2332,6 +2332,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  		/* Wa_22014600077 */
>>  		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>  				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>> +
>> +		/*
>> +		 * Wa_14017066071: mtl-p/m[a0]
>> +		 * Wa_14017654203: mtl-p/m[a0]
>> +		 */
>> +		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>> +				 MTL_DISABLE_SAMPLER_SC_OOO);
>>  	}
>>  
>>  	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> -- 
>> 2.34.1
>>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4a4bab261e66..27b06ff380a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1145,6 +1145,7 @@ 
 #define   ENABLE_SMALLPL			REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
+#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)
 
 #define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 918a271447e2..c52c5f9ad9ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2332,6 +2332,13 @@  rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
+
+		/*
+		 * Wa_14017066071: mtl-p/m[a0]
+		 * Wa_14017654203: mtl-p/m[a0]
+		 */
+		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+				 MTL_DISABLE_SAMPLER_SC_OOO);
 	}
 
 	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||