| Message ID | 20230119140453.3942340-2-abel.vesa@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | sm8550: Add PCIe HC and PHY support | expand |
On 19/01/2023 15:04, Abel Vesa wrote: > Document the QMP PCIe PHY compatible for SM8550. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > > This patchset relies on the following patchset: > https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ > > The v3 of this patchset is: > https://lore.kernel.org/all/20230118005328.2378792-1-abel.vesa@linaro.org/ > > Changes since v3: > * increased the allowed number of resets to allow ncsr reset > * added vdda-qref-supply which is used by pcie1_phy node in MTP dts > * added both compatibles to the allOf:if:then clause to constrain the > number of possible clocks to 5 > > Changes since v2: > * added back the binding compatible update patch > > Changes since v1: > * split all the offsets into separate patches, like Vinod suggested > > .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > index 8a85318d9c92..4b4566f90811 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > @@ -20,6 +20,8 @@ properties: > - qcom,sc8280xp-qmp-gen3x2-pcie-phy > - qcom,sc8280xp-qmp-gen3x4-pcie-phy > - qcom,sm8350-qmp-gen3x1-pcie-phy > + - qcom,sm8550-qmp-gen3x2-pcie-phy > + - qcom,sm8550-qmp-gen4x2-pcie-phy > > reg: > minItems: 1 > @@ -43,16 +45,21 @@ properties: > maxItems: 1 > > resets: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 > > reset-names: > + minItems: 1 > items: > - const: phy > + - const: nocsr I think it is valid only for this phy variant, so please constrain it to 1 entries for all others. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 8a85318d9c92..4b4566f90811 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -20,6 +20,8 @@ properties: - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy reg: minItems: 1 @@ -43,16 +45,21 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 reset-names: + minItems: 1 items: - const: phy + - const: nocsr vdda-phy-supply: true vdda-pll-supply: true + vdda-qref-supply: true + qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array @@ -113,6 +120,8 @@ allOf: contains: enum: - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy then: properties: clocks:
Document the QMP PCIe PHY compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v3 of this patchset is: https://lore.kernel.org/all/20230118005328.2378792-1-abel.vesa@linaro.org/ Changes since v3: * increased the allowed number of resets to allow ncsr reset * added vdda-qref-supply which is used by pcie1_phy node in MTP dts * added both compatibles to the allOf:if:then clause to constrain the number of possible clocks to 5 Changes since v2: * added back the binding compatible update patch Changes since v1: * split all the offsets into separate patches, like Vinod suggested .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)