| Message ID | 167406535137.1455071.12470540886828540377.stgit@djiang5-mobl3.local |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl: Introduce HDM decoder emulation from DVSEC range registers | expand |
On Wed, 18 Jan 2023 11:09:12 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > CXL rev3.0 spec 8.1.3 > > RCDs may not have HDM register blocks. Create fake decoders based on CXL > PCIe DVSEC registers. The DVSEC Range Registers provide the memory range > for these decoder structs. For the RCD, there can be up to 2 decoders > depending on the DVSEC Capability register HDM_count. > > Signed-off-by: Dave Jiang <dave.jiang@intel.com> FWIW Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > v3: > - Drop unrelated bits from patch. (Jonathan) > --- > drivers/cxl/core/hdm.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 86fe1be2e961..cbec955db4c9 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -748,6 +748,13 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, > if (is_endpoint_decoder(&cxld->dev)) > cxled = to_cxl_endpoint_decoder(&cxld->dev); > > + if (!hdm) { > + if (!cxled) > + return -EINVAL; > + > + return cxl_setup_hdm_decoder_from_dvsec(port, cxld, which, info); > + } > + > ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); > base = ioread64_hi_lo(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(which)); > size = ioread64_hi_lo(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(which)); > >
Dave Jiang wrote: > CXL rev3.0 spec 8.1.3 > > RCDs may not have HDM register blocks. Create fake decoders based on CXL > PCIe DVSEC registers. The DVSEC Range Registers provide the memory range > for these decoder structs. For the RCD, there can be up to 2 decoders > depending on the DVSEC Capability register HDM_count. > > Signed-off-by: Dave Jiang <dave.jiang@intel.com> > > --- > v3: > - Drop unrelated bits from patch. (Jonathan) > --- > drivers/cxl/core/hdm.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 86fe1be2e961..cbec955db4c9 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -748,6 +748,13 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, > if (is_endpoint_decoder(&cxld->dev)) > cxled = to_cxl_endpoint_decoder(&cxld->dev); > > + if (!hdm) { > + if (!cxled) I think this wants a dev_dbg() for calling out a failure to setup hdm_decoder registers for a non-endpoint port. Other than that this looks good.
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 86fe1be2e961..cbec955db4c9 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -748,6 +748,13 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, if (is_endpoint_decoder(&cxld->dev)) cxled = to_cxl_endpoint_decoder(&cxld->dev); + if (!hdm) { + if (!cxled) + return -EINVAL; + + return cxl_setup_hdm_decoder_from_dvsec(port, cxld, which, info); + } + ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); base = ioread64_hi_lo(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(which)); size = ioread64_hi_lo(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(which));
CXL rev3.0 spec 8.1.3 RCDs may not have HDM register blocks. Create fake decoders based on CXL PCIe DVSEC registers. The DVSEC Range Registers provide the memory range for these decoder structs. For the RCD, there can be up to 2 decoders depending on the DVSEC Capability register HDM_count. Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- v3: - Drop unrelated bits from patch. (Jonathan) --- drivers/cxl/core/hdm.c | 7 +++++++ 1 file changed, 7 insertions(+)