mbox series

[v7,0/7] KVM: arm64: Normalize cache configuration

Message ID 20230112023852.42012-1-akihiko.odaki@daynix.com (mailing list archive)
Headers show
Series KVM: arm64: Normalize cache configuration | expand

Message

Akihiko Odaki Jan. 12, 2023, 2:38 a.m. UTC
Before this change, the cache configuration of the physical CPU was
exposed to vcpus. This is problematic because the cache configuration a
vcpu sees varies when it migrates between vcpus with different cache
configurations.

Fabricate cache configuration from the sanitized value, which holds the
CTR_EL0 value the userspace sees regardless of which physical CPU it
resides on.

V6 -> V7:
- Make the code to determine cache line more readable.
  Based on Oliver Upton's suggestion.

V5 -> V6:
- Add a comment to get_min_cache_line_size()

V4 -> V5:
- Noted why cache level existence check is unnecessary when fabricating
  CCSIDR_EL1 value.
- Removed FWB check. It is necessary as CLIDR_EL1.{LoUU, LoIUS} on the
  host are {0, 0} if FWB is enabled, and such a CLIDR_EL1 value sets
  the IDC bit of the sanitized CTR_EL0 value, which is already checked.
- Removed UNDEF injection when reading CCSIDR_EL1 with an invalid
  CSSELR_EL1 value.
- Added a check for CLIDR_EL1.{LoUU,LoC,LoUIS} values set from the
  userspace.

V3 -> V4:
- Implemented UNKNOWN system register definition for CCSIDR_EL1
- Added a comment about the relation between CCSIDR_EL1 and FEAT_CCIDX
- Squashed "Normalize cache configuration" and "Allow user to set
  CCSIDR_EL1"
  The intermediate state between them did not make much sense.
- Introduced FIELD_GET to extract CCSIDR_EL1_LineSize.

V2 -> V3:
- Corrected message for patch "Normalize cache configuration"
- Split patch "Normalize cache configuration"
- Added handling for CSSELR_EL1.TnD
- Added code to ignore RES0 in CSSELR_EL1
- Replaced arm64_ftr_reg_ctrel0.sys_val with
  read_sanitised_ftr_reg(SYS_CTR_EL0)
- Fixed vcpu->arch.ccsidr initialziation
- Added CCSIDR_EL1 sanitization
- Added FWB check
- Added a comment for CACHE_TYPE_SEPARATE
- Added MTE tag cache creation code for CLIDR_EL1 fabrication
- Removed CLIDR_EL1 reset code for reset caused by guest
- Added a comment for CCSIDR2

V2: https://lore.kernel.org/lkml/20221211051700.275761-2-akihiko.odaki@daynix.com/
V1: https://lore.kernel.org/lkml/525ff263-90b3-5b12-da31-171b09f9ad1b@daynix.com/

Akihiko Odaki (6):
  arm64/sysreg: Convert CCSIDR_EL1 to automatic generation
  arm64/sysreg: Add CCSIDR2_EL1
  arm64/cache: Move CLIDR macro definitions
  KVM: arm64: Always set HCR_TID2
  KVM: arm64: Mask FEAT_CCIDX
  KVM: arm64: Normalize cache configuration

Marc Zyngier (1):
  arm64: Allow the definition of UNKNOWN system register fields

 arch/arm64/include/asm/cache.h             |   9 +
 arch/arm64/include/asm/kvm_arm.h           |   3 +-
 arch/arm64/include/asm/kvm_emulate.h       |   4 -
 arch/arm64/include/asm/kvm_host.h          |   6 +-
 arch/arm64/include/asm/sysreg.h            |   1 -
 arch/arm64/kernel/cacheinfo.c              |   5 -
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h |   2 -
 arch/arm64/kvm/reset.c                     |   1 +
 arch/arm64/kvm/sys_regs.c                  | 274 +++++++++++++--------
 arch/arm64/tools/gen-sysreg.awk            |  20 +-
 arch/arm64/tools/sysreg                    |  17 ++
 11 files changed, 230 insertions(+), 112 deletions(-)

Comments

Oliver Upton Jan. 23, 2023, 8:24 p.m. UTC | #1
On Thu, 12 Jan 2023 11:38:45 +0900, Akihiko Odaki wrote:
> Before this change, the cache configuration of the physical CPU was
> exposed to vcpus. This is problematic because the cache configuration a
> vcpu sees varies when it migrates between vcpus with different cache
> configurations.
> 
> Fabricate cache configuration from the sanitized value, which holds the
> CTR_EL0 value the userspace sees regardless of which physical CPU it
> resides on.
> 
> [...]

Applied to kvmarm/next, thanks!

[1/7] arm64: Allow the definition of UNKNOWN system register fields
      https://git.kernel.org/kvmarm/kvmarm/c/e2c0b51f1c9d
[2/7] arm64/sysreg: Convert CCSIDR_EL1 to automatic generation
      https://git.kernel.org/kvmarm/kvmarm/c/d1a0eb124c44
[3/7] arm64/sysreg: Add CCSIDR2_EL1
      https://git.kernel.org/kvmarm/kvmarm/c/8f407d6a15f3
[4/7] arm64/cache: Move CLIDR macro definitions
      https://git.kernel.org/kvmarm/kvmarm/c/805e6ec1c5e0
[5/7] KVM: arm64: Always set HCR_TID2
      https://git.kernel.org/kvmarm/kvmarm/c/8cc6dedaff42
[6/7] KVM: arm64: Mask FEAT_CCIDX
      https://git.kernel.org/kvmarm/kvmarm/c/bf48040cd9b0
[7/7] KVM: arm64: Normalize cache configuration
      https://git.kernel.org/kvmarm/kvmarm/c/7af0c2534f4c

--
Best,
Oliver