| Message ID | 20230123225700.2224063-5-kim.phillips@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/cpu, kvm: Support AMD Automatic IBRS | expand |
On Mon, Jan 23, 2023, Kim Phillips wrote: > The LFENCE always serializing feature bit was defined as scattered > LFENCE_RDTSC and its native leaf bit position open-coded for KVM. > Add it to its newly added CPUID leaf 0x80000021 EAX proper. > > Drop the bit description comments now it's more self-describing. > > Also, in amd_init(), don't bother setting DE_CFG[1] any more. > > Signed-off-by: Kim Phillips <kim.phillips@amd.com> > --- > arch/x86/include/asm/cpufeatures.h | 3 ++- > arch/x86/kernel/cpu/amd.c | 2 +- > arch/x86/kvm/cpuid.c | 4 ++-- > 3 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 7f0fb894e432..4f22d828c753 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -97,7 +97,7 @@ > #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ > #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ > #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ > -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ > +/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ > #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ > #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ > #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ > @@ -430,6 +430,7 @@ > > /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ > #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ > +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ > > /* > * BUG word(s) > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > index f769d6d08b43..208c2ce8598a 100644 > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -956,7 +956,7 @@ static void init_amd(struct cpuinfo_x86 *c) > > init_amd_cacheinfo(c); > > - if (cpu_has(c, X86_FEATURE_XMM2)) { > + if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { > /* > * Use LFENCE for execution serialization. On families which > * don't have that MSR, LFENCE is already serializing. > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 13bd2769fa5a..601eeb03ebc9 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -742,11 +742,11 @@ void kvm_set_cpu_caps(void) > F(SME_COHERENT)); > > kvm_cpu_cap_mask(CPUID_8000_0021_EAX, > - F(NO_NESTED_DATA_BP) | 0 /* SmmPgCfgLock */ | > + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | > BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ > ); > if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) > - kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */; > + kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); Now that LFENCE_RDTSC is in its proper place, the kernel's set_cpu_cap() will effectively sythesize the feature for KVM. I.e. this patch can simply delete the synthesis of the feature. > if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) > kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */; > kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */; > -- > 2.34.1 >
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7f0fb894e432..4f22d828c753 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -97,7 +97,7 @@ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ +/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ @@ -430,6 +430,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f769d6d08b43..208c2ce8598a 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -956,7 +956,7 @@ static void init_amd(struct cpuinfo_x86 *c) init_amd_cacheinfo(c); - if (cpu_has(c, X86_FEATURE_XMM2)) { + if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { /* * Use LFENCE for execution serialization. On families which * don't have that MSR, LFENCE is already serializing. diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 13bd2769fa5a..601eeb03ebc9 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,11 +742,11 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - F(NO_NESTED_DATA_BP) | 0 /* SmmPgCfgLock */ | + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ ); if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) - kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */; + kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */; kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;
The LFENCE always serializing feature bit was defined as scattered LFENCE_RDTSC and its native leaf bit position open-coded for KVM. Add it to its newly added CPUID leaf 0x80000021 EAX proper. Drop the bit description comments now it's more self-describing. Also, in amd_init(), don't bother setting DE_CFG[1] any more. Signed-off-by: Kim Phillips <kim.phillips@amd.com> --- arch/x86/include/asm/cpufeatures.h | 3 ++- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kvm/cpuid.c | 4 ++-- 3 files changed, 5 insertions(+), 4 deletions(-)