| Message ID | 20230113160651.51201-2-nick.hawkins@hpe.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: Add GXP Fan and SPI controllers | expand |
On Fri, Jan 13, 2023, at 17:06, nick.hawkins@hpe.com wrote: > From: Nick Hawkins <nick.hawkins@hpe.com> > > Reorganize the base address of AHB to accommodate the SPI and fan driver > register requirements. Add the hpe,gxp-spifi and hpe,gxp-fan-ctrl > compatibles. Add comments to make the register range more clear. The changelog describes three separate things, which usually means you should split up the patch into three smaller ones to make it easier to review. It sounds like the third one is no longer part of the patch anyway. > @@ -52,76 +52,102 @@ > cache-level = <2>; > }; > > - ahb@c0000000 { > + ahb@80000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0x0 0xc0000000 0x30000000>; > + ranges = <0x0 0x80000000 0xf000000>, > + <0x40000000 0xc0000000 0x40000000>; In the changelog text for the first patch that moves the ranges down, it would make sense to describe why this specific move is done. "to accommodate the SPI and fan driver register requirements" does not actually tell me why it was first thought that the bus starts at 0xc0000000 but now starts at 0x80000000 and has a weird hole. Please explain how you determined the location of the hole and the 0x80000000 offset. Are these from the datasheet, from the hardware design or did you make them up because you thought this is what I want? > dma-ranges; Having a 1:1 translation for DMA addresses is actually an indication that the MMIO addresses on the bus might also be directly mapped, rather than offset: If AHB addresses 0x0-0x80000000 refer to the local MMIO registers, there is no more room for addressing RAM in the same addresses. > - vic1: interrupt-controller@80f00000 { > + vic1: interrupt-controller@f00000 { > compatible = "arm,pl192-vic"; > - reg = <0x80f00000 0x1000>; > + reg = <0xf00000 0x1000>; > interrupt-controller; > #interrupt-cells = <1>; > }; Since you said that the earlier version of this was broken, it would also make sense to split this bit out into a separate bugfix patch, or at least describe it in the changelog text. Arnd
> > @@ -52,76 +52,102 @@ > > cache-level = <2>; > > }; > > > > - ahb@c0000000 { > > + ahb@80000000 { > > compatible = "simple-bus"; > address-cells = <1>; > > #size-cells = <1>; > > - ranges = <0x0 0xc0000000 0x30000000>; > > + ranges = <0x0 0x80000000 0xf000000>, > > + <0x40000000 0xc0000000 0x40000000>; > In the changelog text for the first patch that moves the > ranges down, it would make sense to describe why this specific > move is done. "to accommodate the SPI and fan driver > register requirements" does not actually tell me why it was > first thought that the bus starts at 0xc0000000 but now starts > at 0x80000000 and has a weird hole. > Please explain how you determined the location of the hole and > the 0x80000000 offset. Are these from the datasheet, from > the hardware design or did you make them up because you thought > this is what I want? Greetings Arnd, These are from a specification; I was mapping all the registers that were not host related, but we need to include those now. The AHB section of registers indeed does start at 0x80000000. The layout of AHB is as follows: 0x80000000 - 0xa0000000 are host registers Then there is a section of registers we do not currently want to access as it is reserved which is mapped from: 0xa0000000 - 0xc0000000 Then we have more registers ranging from 0xc0000000 - 0xffff0000 that we will be accessing. Hence, I believe the proper ranges for this would be: ranges = <0x0 0x80000000 0x20000000 0x40000000 0xc0000000 0x3fff0000>; /* 0x80000000 - 0xa0000000 and 0xc0000000 - 0xffff0000 */ > > dma-ranges; > Having a 1:1 translation for DMA addresses is actually an indication > that the MMIO addresses on the bus might also be directly > mapped, rather than offset: If AHB addresses 0x0-0x80000000 > refer to the local MMIO registers, there is no more room > for addressing RAM in the same addresses. I believe that this property should no longer be present here. DMA is in the area before 0x80000000. Thanks, -Nick Hawkins
diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts index 3a7382ce40ef..d49dcef95c5c 100644 --- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts +++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts @@ -24,3 +24,61 @@ reg = <0x40000000 0x20000000>; }; }; + +&spifi { + status = "okay"; + flash@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + label = "u-boot"; + reg = <0x0 0x60000>; + }; + + u-boot-env@60000 { + label = "u-boot-env"; + reg = <0x60000 0x20000>; + }; + + kernel@80000 { + label = "kernel"; + reg = <0x80000 0x4c0000>; + }; + + rofs@540000 { + label = "rofs"; + reg = <0x540000 0x1740000>; + }; + + rwfs@1c80000 { + label = "rwfs"; + reg = <0x1c80000 0x250000>; + }; + + section@1ed0000{ + label = "section"; + reg = <0x1ed0000 0x130000>; + }; + }; + }; + flash@1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + host-prime@0 { + label = "host-prime"; + reg = <0x0 0x02000000>; + }; + + host-second@2000000 { + label = "host-second"; + reg = <0x02000000 0x02000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi index cf735b3c4f35..4d195d466087 100644 --- a/arch/arm/boot/dts/hpe-gxp.dtsi +++ b/arch/arm/boot/dts/hpe-gxp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree file for HPE GXP + * Device Tree for HPE */ /dts-v1/; @@ -52,76 +52,102 @@ cache-level = <2>; }; - ahb@c0000000 { + ahb@80000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0xc0000000 0x30000000>; + ranges = <0x0 0x80000000 0xf000000>, + <0x40000000 0xc0000000 0x40000000>; dma-ranges; - vic0: interrupt-controller@eff0000 { + spifi: spi@40000200 { + compatible = "hpe,gxp-spifi"; + reg = <0x40000200 0x80>, <0x4000c000 0x100>, <0x78000000 0x7ff0000>; + interrupts = <20>; + interrupt-parent = <&vic0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + }; + }; + + vic0: interrupt-controller@4eff0000 { compatible = "arm,pl192-vic"; - reg = <0xeff0000 0x1000>; + reg = <0x4eff0000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; - vic1: interrupt-controller@80f00000 { + vic1: interrupt-controller@f00000 { compatible = "arm,pl192-vic"; - reg = <0x80f00000 0x1000>; + reg = <0xf00000 0x1000>; interrupt-controller; #interrupt-cells = <1>; }; - uarta: serial@e0 { + uarta: serial@400000e0 { compatible = "ns16550a"; - reg = <0xe0 0x8>; + reg = <0x400000e0 0x8>; interrupts = <17>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - uartb: serial@e8 { + uartb: serial@400000e8 { compatible = "ns16550a"; - reg = <0xe8 0x8>; + reg = <0x400000e8 0x8>; interrupts = <18>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - uartc: serial@f0 { + uartc: serial@400000f0 { compatible = "ns16550a"; - reg = <0xf0 0x8>; + reg = <0x400000f0 0x8>; interrupts = <19>; interrupt-parent = <&vic0>; clock-frequency = <1846153>; reg-shift = <0>; }; - usb0: usb@efe0000 { + usb0: usb@4efe0000 { compatible = "hpe,gxp-ehci", "generic-ehci"; - reg = <0xefe0000 0x100>; + reg = <0x4efe0000 0x100>; interrupts = <7>; interrupt-parent = <&vic0>; }; - st: timer@80 { + st: timer@40000080 { compatible = "hpe,gxp-timer"; - reg = <0x80 0x16>; + reg = <0x40000080 0x16>; interrupts = <0>; interrupt-parent = <&vic0>; clocks = <&iopclk>; clock-names = "iop"; }; - usb1: usb@efe0100 { + usb1: usb@4efe0100 { compatible = "hpe,gxp-ohci", "generic-ohci"; - reg = <0xefe0100 0x110>; + reg = <0x4efe0100 0x110>; interrupts = <6>; interrupt-parent = <&vic0>; }; + + fan-controller@40000c10 { + compatible = "hpe,gxp-fan-ctrl"; + reg = <0x40000c10 0x8>, <0x51000027 0x06>, <0x200070 0x04>; + reg-names = "base", "pl", "fn2"; + }; }; }; };