| Message ID | 20230115154953.831-10-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | riscv: improve boot time isa extensions handling | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/patch_count | success | Link |
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 13 and now 13 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 2050 this patch: 2050 |
| conchuod/alphanumeric_selects | success | Out of order selects before the patch: 57 and now 57 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 4 this patch: 4 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | warning | CHECK: Macro argument 'f' may be better as '(f)' to avoid precedence issues WARNING: unnecessary whitespace before a quoted newline |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Sun, Jan 15, 2023 at 11:49:49PM +0800, Jisheng Zhang wrote: > Instead of using absolute addresses for both the old instrucions and > the alternative instructions, use offsets relative to the alt_entry > values. So this not only cuts the size of the alternative entry, but > also meets the prerequisite for patching alternatives in the vDSO, > since absolute alternative entries are subject to dynamic relocation, > which is incompatible with the vDSO building. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > +/* add the relative offset to the address of the offset to get the absolute address */ > +#define __ALT_PTR(a, f) ((void *)&(a)->f + (a)->f) > +#define ALT_OLD_PTR(a) __ALT_PTR(a, old_offset) > +#define ALT_ALT_PTR(a) __ALT_PTR(a, alt_offset) LGTM, thanks for doing that! Certainly makes things more understandable. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > + oldptr = ALT_OLD_PTR(alt); > + altptr = ALT_ALT_PTR(alt); > if (!__riscv_isa_extension_available(NULL, alt->errata_id)) > continue; > One minor nit, the oldptr/altptr assignments could go down here, below the if/continue, right? Obviously don't respin for that though! > - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); > - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, > - alt->old_ptr - alt->alt_ptr); > + patch_text_nosync(oldptr, altptr, alt->alt_len); > + riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); > } > } > #endif
On Sun, Jan 15, 2023 at 11:49:49PM +0800, Jisheng Zhang wrote: ... > #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ > - RISCV_PTR " " oldptr "\n" \ > - RISCV_PTR " " newptr "\n" \ > - REG_ASM " " vendor_id "\n" \ > - REG_ASM " " newlen "\n" \ > - ".word " errata_id "\n" > + ".4byte ((" oldptr ") - .) \n" \ > + ".4byte ((" newptr ") - .) \n" \ > + ".2byte " vendor_id "\n" \ > + ".2byte " newlen "\n" \ > + ".4byte " errata_id "\n" > Hi Jisheng, This patch breaks loading the KVM module for me. I got "kvm: Unknown relocation type 34". My guess is that these 2 byte fields are inspiring the compiler to emit 16-bit relocation types. The patch below fixes things for me. If you agree with fixing it this way, rather than changing something in alternatives, like not using 2 byte fields, then please pick the below patch up in your series. Thanks, drew From 4d203697aa745a0cd3a9217d547a9fb7fa2a87c7 Mon Sep 17 00:00:00 2001 From: Andrew Jones <ajones@ventanamicro.com> Date: Fri, 20 Jan 2023 19:05:44 +0100 Subject: [PATCH] riscv: module: Add ADD16 and SUB16 rela types Content-type: text/plain To prepare for 16-bit relocation types to be emitted in alternatives add support for ADD16 and SUB16. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- arch/riscv/kernel/module.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 76f4b9c2ec5b..7c651d55fcbd 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -268,6 +268,13 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } +static int apply_r_riscv_add16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location += (u16)v; + return 0; +} + static int apply_r_riscv_add32_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -282,6 +289,13 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location -= (u16)v; + return 0; +} + static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -315,8 +329,10 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, [R_RISCV_CALL] = apply_r_riscv_call_rela, [R_RISCV_RELAX] = apply_r_riscv_relax_rela, [R_RISCV_ALIGN] = apply_r_riscv_align_rela, + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, [R_RISCV_ADD32] = apply_r_riscv_add32_rela, [R_RISCV_ADD64] = apply_r_riscv_add64_rela, + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, };
On Fri, Jan 20, 2023 at 07:34:18PM +0100, Andrew Jones wrote: > On Sun, Jan 15, 2023 at 11:49:49PM +0800, Jisheng Zhang wrote: > ... > > #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ > > - RISCV_PTR " " oldptr "\n" \ > > - RISCV_PTR " " newptr "\n" \ > > - REG_ASM " " vendor_id "\n" \ > > - REG_ASM " " newlen "\n" \ > > - ".word " errata_id "\n" > > + ".4byte ((" oldptr ") - .) \n" \ > > + ".4byte ((" newptr ") - .) \n" \ > > + ".2byte " vendor_id "\n" \ > > + ".2byte " newlen "\n" \ > > + ".4byte " errata_id "\n" > > > > Hi Jisheng, > > This patch breaks loading the KVM module for me. I got "kvm: Unknown > relocation type 34". My guess is that these 2 byte fields are inspiring > the compiler to emit 16-bit relocation types. The patch below fixes > things for me. If you agree with fixing it this way, rather than > changing something in alternatives, like not using 2 byte fields, > then please pick the below patch up in your series. Hi Jisheng, I'm poking again on this as I see this series is now working its way to be merged into for-next. I'd rather avoid the bisection breakage which will be present if we fix this issue afterwards by having a v5 merged which addresses the issue in the correct patch order. Thanks, drew > > From 4d203697aa745a0cd3a9217d547a9fb7fa2a87c7 Mon Sep 17 00:00:00 2001 > From: Andrew Jones <ajones@ventanamicro.com> > Date: Fri, 20 Jan 2023 19:05:44 +0100 > Subject: [PATCH] riscv: module: Add ADD16 and SUB16 rela types > Content-type: text/plain > > To prepare for 16-bit relocation types to be emitted in alternatives > add support for ADD16 and SUB16. > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > --- > arch/riscv/kernel/module.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c > index 76f4b9c2ec5b..7c651d55fcbd 100644 > --- a/arch/riscv/kernel/module.c > +++ b/arch/riscv/kernel/module.c > @@ -268,6 +268,13 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, > return -EINVAL; > } > > +static int apply_r_riscv_add16_rela(struct module *me, u32 *location, > + Elf_Addr v) > +{ > + *(u16 *)location += (u16)v; > + return 0; > +} > + > static int apply_r_riscv_add32_rela(struct module *me, u32 *location, > Elf_Addr v) > { > @@ -282,6 +289,13 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, > return 0; > } > > +static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, > + Elf_Addr v) > +{ > + *(u16 *)location -= (u16)v; > + return 0; > +} > + > static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, > Elf_Addr v) > { > @@ -315,8 +329,10 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, > [R_RISCV_CALL] = apply_r_riscv_call_rela, > [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > }; > -- > 2.39.0 >
On Fri, Jan 20, 2023 at 07:34:18PM +0100, Andrew Jones wrote: > On Sun, Jan 15, 2023 at 11:49:49PM +0800, Jisheng Zhang wrote: > ... > > #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ > > - RISCV_PTR " " oldptr "\n" \ > > - RISCV_PTR " " newptr "\n" \ > > - REG_ASM " " vendor_id "\n" \ > > - REG_ASM " " newlen "\n" \ > > - ".word " errata_id "\n" > > + ".4byte ((" oldptr ") - .) \n" \ > > + ".4byte ((" newptr ") - .) \n" \ > > + ".2byte " vendor_id "\n" \ > > + ".2byte " newlen "\n" \ > > + ".4byte " errata_id "\n" > > > > Hi Jisheng, > > This patch breaks loading the KVM module for me. I got "kvm: Unknown > relocation type 34". My guess is that these 2 byte fields are inspiring > the compiler to emit 16-bit relocation types. The patch below fixes > things for me. If you agree with fixing it this way, rather than > changing something in alternatives, like not using 2 byte fields, > then please pick the below patch up in your series. > > Thanks, > drew > > From 4d203697aa745a0cd3a9217d547a9fb7fa2a87c7 Mon Sep 17 00:00:00 2001 > From: Andrew Jones <ajones@ventanamicro.com> > Date: Fri, 20 Jan 2023 19:05:44 +0100 > Subject: [PATCH] riscv: module: Add ADD16 and SUB16 rela types > Content-type: text/plain > > To prepare for 16-bit relocation types to be emitted in alternatives > add support for ADD16 and SUB16. > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> For the fixup: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks! > --- > arch/riscv/kernel/module.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c > index 76f4b9c2ec5b..7c651d55fcbd 100644 > --- a/arch/riscv/kernel/module.c > +++ b/arch/riscv/kernel/module.c > @@ -268,6 +268,13 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, > return -EINVAL; > } > > +static int apply_r_riscv_add16_rela(struct module *me, u32 *location, > + Elf_Addr v) > +{ > + *(u16 *)location += (u16)v; > + return 0; > +} > + > static int apply_r_riscv_add32_rela(struct module *me, u32 *location, > Elf_Addr v) > { > @@ -282,6 +289,13 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, > return 0; > } > > +static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, > + Elf_Addr v) > +{ > + *(u16 *)location -= (u16)v; > + return 0; > +} > + > static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, > Elf_Addr v) > { > @@ -315,8 +329,10 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, > [R_RISCV_CALL] = apply_r_riscv_call_rela, > [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > }; > -- > 2.39.0 >
On Thu, Jan 26, 2023 at 08:09:30AM +0100, Andrew Jones wrote: > On Fri, Jan 20, 2023 at 07:34:18PM +0100, Andrew Jones wrote: > > On Sun, Jan 15, 2023 at 11:49:49PM +0800, Jisheng Zhang wrote: > > ... > > > #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ > > > - RISCV_PTR " " oldptr "\n" \ > > > - RISCV_PTR " " newptr "\n" \ > > > - REG_ASM " " vendor_id "\n" \ > > > - REG_ASM " " newlen "\n" \ > > > - ".word " errata_id "\n" > > > + ".4byte ((" oldptr ") - .) \n" \ > > > + ".4byte ((" newptr ") - .) \n" \ > > > + ".2byte " vendor_id "\n" \ > > > + ".2byte " newlen "\n" \ > > > + ".4byte " errata_id "\n" > > > > > > > Hi Jisheng, > > > > This patch breaks loading the KVM module for me. I got "kvm: Unknown > > relocation type 34". My guess is that these 2 byte fields are inspiring > > the compiler to emit 16-bit relocation types. The patch below fixes > > things for me. If you agree with fixing it this way, rather than > > changing something in alternatives, like not using 2 byte fields, > > then please pick the below patch up in your series. > > Hi Jisheng, > > I'm poking again on this as I see this series is now working its way > to be merged into for-next. I'd rather avoid the bisection breakage > which will be present if we fix this issue afterwards by having a > v5 merged which addresses the issue in the correct patch order. Hi Andrew, Sorry for being late. I was on holiday in the past few days. I'm cooking v5 and will send out it soon. Thanks so much > > Thanks, > drew > > > > > From 4d203697aa745a0cd3a9217d547a9fb7fa2a87c7 Mon Sep 17 00:00:00 2001 > > From: Andrew Jones <ajones@ventanamicro.com> > > Date: Fri, 20 Jan 2023 19:05:44 +0100 > > Subject: [PATCH] riscv: module: Add ADD16 and SUB16 rela types > > Content-type: text/plain > > > > To prepare for 16-bit relocation types to be emitted in alternatives > > add support for ADD16 and SUB16. > > > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> > > --- > > arch/riscv/kernel/module.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c > > index 76f4b9c2ec5b..7c651d55fcbd 100644 > > --- a/arch/riscv/kernel/module.c > > +++ b/arch/riscv/kernel/module.c > > @@ -268,6 +268,13 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, > > return -EINVAL; > > } > > > > +static int apply_r_riscv_add16_rela(struct module *me, u32 *location, > > + Elf_Addr v) > > +{ > > + *(u16 *)location += (u16)v; > > + return 0; > > +} > > + > > static int apply_r_riscv_add32_rela(struct module *me, u32 *location, > > Elf_Addr v) > > { > > @@ -282,6 +289,13 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, > > return 0; > > } > > > > +static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, > > + Elf_Addr v) > > +{ > > + *(u16 *)location -= (u16)v; > > + return 0; > > +} > > + > > static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, > > Elf_Addr v) > > { > > @@ -315,8 +329,10 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, > > [R_RISCV_CALL] = apply_r_riscv_call_rela, > > [R_RISCV_RELAX] = apply_r_riscv_relax_rela, > > [R_RISCV_ALIGN] = apply_r_riscv_align_rela, > > + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, > > [R_RISCV_ADD32] = apply_r_riscv_add32_rela, > > [R_RISCV_ADD64] = apply_r_riscv_add64_rela, > > + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, > > [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, > > [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, > > }; > > -- > > 2.39.0 > >
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 1031038423e7..ef9a4eec0dba 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -107,7 +107,8 @@ void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, tmp = (1U << alt->errata_id); if (cpu_req_errata & tmp) { - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), + alt->alt_len); cpu_apply_errata |= tmp; } } diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index fac5742d1c1e..c0bea5c94128 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -87,6 +87,7 @@ void __init_or_module thead_errata_patch_func(struct alt_entry *begin, struct al struct alt_entry *alt; u32 cpu_req_errata = thead_errata_probe(stage, archid, impid); u32 tmp; + void *oldptr, *altptr; for (alt = begin; alt < end; alt++) { if (alt->vendor_id != THEAD_VENDOR_ID) @@ -96,12 +97,16 @@ void __init_or_module thead_errata_patch_func(struct alt_entry *begin, struct al tmp = (1U << alt->errata_id); if (cpu_req_errata & tmp) { + oldptr = ALT_OLD_PTR(alt); + altptr = ALT_ALT_PTR(alt); + /* On vm-alternatives, the mmu isn't running yet */ if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) - memcpy((void *)__pa_symbol(alt->old_ptr), - (void *)__pa_symbol(alt->alt_ptr), alt->alt_len); + memcpy((void *)__pa_symbol(oldptr), + (void *)__pa_symbol(altptr), + alt->alt_len); else - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + patch_text_nosync(oldptr, altptr, alt->alt_len); } } diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 7226e2462584..cc6a81c00f2f 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -7,11 +7,11 @@ #ifdef __ASSEMBLY__ .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len - RISCV_PTR \oldptr - RISCV_PTR \newptr - REG_ASM \vendor_id - REG_ASM \new_len - .word \errata_id + .4byte \oldptr - . + .4byte \newptr - . + .2byte \vendor_id + .2byte \new_len + .4byte \errata_id .endm .macro ALT_NEW_CONTENT vendor_id, errata_id, enable = 1, new_c : vararg @@ -59,11 +59,11 @@ #include <linux/stringify.h> #define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ - RISCV_PTR " " oldptr "\n" \ - RISCV_PTR " " newptr "\n" \ - REG_ASM " " vendor_id "\n" \ - REG_ASM " " newlen "\n" \ - ".word " errata_id "\n" + ".4byte ((" oldptr ") - .) \n" \ + ".4byte ((" newptr ") - .) \n" \ + ".2byte " vendor_id "\n" \ + ".2byte " newlen "\n" \ + ".4byte " errata_id "\n" #define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \ ".if " __stringify(enable) " == 1\n" \ diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 1bd4027d34ca..b8648d4f2ac1 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -23,6 +23,11 @@ #define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */ #define RISCV_ALTERNATIVES_EARLY_BOOT 2 /* alternatives applied before mmu start */ +/* add the relative offset to the address of the offset to get the absolute address */ +#define __ALT_PTR(a, f) ((void *)&(a)->f + (a)->f) +#define ALT_OLD_PTR(a) __ALT_PTR(a, old_offset) +#define ALT_ALT_PTR(a) __ALT_PTR(a, alt_offset) + void __init apply_boot_alternatives(void); void __init apply_early_boot_alternatives(void); void apply_module_alternatives(void *start, size_t length); @@ -31,12 +36,12 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len, int patch_offset); struct alt_entry { - void *old_ptr; /* address of original instruciton or data */ - void *alt_ptr; /* address of replacement instruction or data */ - unsigned long vendor_id; /* cpu vendor id */ - unsigned long alt_len; /* The replacement size */ - unsigned int errata_id; /* The errata id */ -} __packed; + s32 old_offset; /* offset relative to original instruction or data */ + s32 alt_offset; /* offset relative to replacement instruction or data */ + u16 vendor_id; /* cpu vendor id */ + u16 alt_len; /* The replacement size */ + u32 errata_id; /* The errata id */ +}; struct errata_checkfunc_id { unsigned long vendor_id; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6db8b31d9149..50cfbbbecaa7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -280,6 +280,7 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, unsigned int stage) { struct alt_entry *alt; + void *oldptr, *altptr; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -293,12 +294,13 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, continue; } + oldptr = ALT_OLD_PTR(alt); + altptr = ALT_ALT_PTR(alt); if (!__riscv_isa_extension_available(NULL, alt->errata_id)) continue; - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); - riscv_alternative_fix_offsets(alt->old_ptr, alt->alt_len, - alt->old_ptr - alt->alt_ptr); + patch_text_nosync(oldptr, altptr, alt->alt_len); + riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); } } #endif